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Data processor, method, device and chip

A data processor and data technology, applied in the computer field, can solve the problems of increasing the power consumption of the data processor and reducing the versatility of the data processor

Pending Publication Date: 2021-06-25
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, existing data processors can only perform multiplication and accumulation operations on data with the same bit width, which reduces the versatility of the data processor
In addition, in the prior art, multiple multiplication results need to be accumulated separately to realize the multiplication and accumulation operation, thereby increasing the power consumption of the data processor

Method used

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  • Data processor, method, device and chip
  • Data processor, method, device and chip
  • Data processor, method, device and chip

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Embodiment Construction

[0095] In order to make the purpose, technical solutions and advantages of the present application, the present application will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are intended to explain the present application and is not intended to limit the present application.

[0096] The data processor provided herein can be applied to the AI ​​chip, field programmable gate array, FPGA chip, or other hardware circuit devices for multiplication operation processing or multiplication portfolio processing, this data Structure of the processor, such as figure 1 Indicated.

[0097] Such as figure 1 Distance figure 1 A structural diagram of a data processor provided for one embodiment. Such as figure 1 As shown, the data processor comprising: a first multiplication circuit 01, multiplication circuit 02, and the second partial-product switching circuit 03, the first mu...

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Abstract

The invention provides a data processor, a method, a device and a chip. The data processor comprises a first multiplication circuit, a second multiplication circuit and a partial product switching circuit, the first multiplication circuit comprises a first improved regular signed number CSD coding branch, a first selection branch and a first improved compression branch, The second multiplication circuit comprises a second improved CSD coding branch, a second selection branch and a second improved compression branch; Each of the first improved compression branch and the second improved compression branch comprises a 4-2 compressor, and each 4-2 compressor comprises a selection circuit and a full adder; The data processor not only can realize multiplication operation, but also can realize multiply-accumulate operation, so that the universality of the data processor is improved; Besides, the data processor can complete the multiply-accumulate operation without carrying out the accumulate operation on the multiplication operation result again, and the multiply-accumulate operation or the multiplication operation can be directly realized only through one operation process, so that the power consumption of the data processor is reduced.

Description

Technical field [0001] The present application relates to the field of computer technology, and more particularly to a data processor, method, apparatus, and chip. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of all kinds of artificial intelligencers (AI) chips is also increasing in high performance data processors, of which data processors are multipliers, adders or multiplication accumulator. As one of the algorithms widely applied by the intelligent chip, the neural network algorithm is used by multipliers to multiply the intensive accumulation operation in a neural network algorithm. [0003] Typically, the data processor is a multiplier multiplier that uses multiple identical input data bit wide or different data bit wide, and obtains multiple multiplication operations, and then the plurality of multiplier calculations are accumulated by the plurality of multiplication results. Target multiplication res...

Claims

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Application Information

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IPC IPC(8): G06N3/08G06N3/063
CPCG06N3/082G06N3/063Y02D10/00
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD