Phase-locked detection device, phase-locked detection method and phase-locked loop

A detection device and a phase-locked technology, applied in the field of phase-locked loops, can solve the problems of unreliable results, inability to detect short pulses, and inability to identify short-term loss of lock.

Pending Publication Date: 2021-07-30

杭州雄迈集成电路技术股份有限公司

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AI-Extracted Technical Summary

Problems solved by technology

[0005] If the current digital detection method encounters the loss of the reference clock, the need to drive a more accurate VCXO, and the high-frequency low-frequency equalization, the result will be unreliable, and the short-term loss of lock cannot be identified, and the sensitivity is relatively low. Cannot detect short...

Abstract

The invention provides a phase-locked detection device, a phase-locked detection method and a phase-locked loop. The phase-locked detection device comprises a reference pulse generation circuit, a feedback pulse generation circuit, a reset circuit, a reset signal generation circuit, a pulse acquisition circuit and a phase-locked judgment circuit, a reference clock is input into the reference pulse generation circuit to generate a reference pulse, and the reference pulse is input into the pulse acquisition circuit and the reset signal generation circuit; the feedback clock is input into the feedback pulse generation circuit, the feedback pulse generation circuit outputs feedback pulses, and the feedback pulses are input into the pulse acquisition circuit; the pulse acquisition circuit takes a feedback pulse as clock end input, takes a reference pulse as counting end input, and outputs a phase-locked enable signal; the phase-locked enable signal is output to the phase-locked judgment circuit, and the phase-locked judgment circuit outputs a locking signal after counting reaches a preset value. The scheme provides the detection device which is simple in precision and simple in structure.

Application Domain

Pulse automatic control

Technology Topic

Phase lockingPhase-locked loop +2

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Examples

Experimental program(1)

Example Embodiment

[0094] Example 2:

[0095] This embodiment provides a phase-locked detection method, comprising the following steps:

[0096] Obtain the reference clock of the phase-locked loop and the frequency-divided signal of the feedback clock;

[0097] Performing multi-bit logic operations on the two-frequency signal to obtain a reference pulse and a feedback pulse;

[0098] Take the feedback pulse as the trigger condition to collect the reference pulse and obtain the phase-locking enable signal;

[0099] The phase lock enable signal is executed with a counter, and a lock result is output.

[0100] A period reset signal is obtained by performing multi-bit logic operations on the frequency-divided signal, and the feedback pulse is controlled by the period reset signal.

[0101] In addition, it should be noted that in Example 1, about Figure 2-5The descriptions of the first AND gate, the second AND gate, the first logic signal, the second logic signal, etc., do not represent the same components in actual physical space locations, and are used for convenience of description here only.

PUM

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