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Phase-locked detection device, phase-locked detection method and phase-locked loop

A detection device and a phase-locked technology, applied in the field of phase-locked loops, can solve the problems of unreliable results, inability to detect short pulses, and inability to identify short-term loss of lock.

Pending Publication Date: 2021-07-30
杭州雄迈集成电路技术股份有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] If the current digital detection method encounters the loss of the reference clock, the need to drive a more accurate VCXO, and the high-frequency low-frequency equalization, the result will be unreliable, and the short-term loss of lock cannot be identified, and the sensitivity is relatively low. Cannot detect short pulses
[0006] The problem with the current analog detection method is that although compared with digital detection, it will be reflected in the advantages of frequency discrimination at high frequencies, but the design method is cumbersome, and it is necessary to calculate the filter capacitor, pull-up and series capacitors.

Method used

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  • Phase-locked detection device, phase-locked detection method and phase-locked loop
  • Phase-locked detection device, phase-locked detection method and phase-locked loop
  • Phase-locked detection device, phase-locked detection method and phase-locked loop

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Embodiment 2

[0095] This embodiment provides a phase-locked detection method, comprising the following steps:

[0096] Obtain the reference clock of the phase-locked loop and the frequency-divided signal of the feedback clock;

[0097] Performing multi-bit logic operations on the two-frequency signal to obtain a reference pulse and a feedback pulse;

[0098] Take the feedback pulse as the trigger condition to collect the reference pulse and obtain the phase-locking enable signal;

[0099] The phase lock enable signal is executed with a counter, and a lock result is output.

[0100] A period reset signal is obtained by performing multi-bit logic operations on the frequency-divided signal, and the feedback pulse is controlled by the period reset signal.

[0101] In addition, it should be noted that in Example 1, about Figure 2-5The descriptions of the first AND gate, the second AND gate, the first logic signal, the second logic signal, etc., do not represent the same components in actual...

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Abstract

The invention provides a phase-locked detection device, a phase-locked detection method and a phase-locked loop. The phase-locked detection device comprises a reference pulse generation circuit, a feedback pulse generation circuit, a reset circuit, a reset signal generation circuit, a pulse acquisition circuit and a phase-locked judgment circuit, a reference clock is input into the reference pulse generation circuit to generate a reference pulse, and the reference pulse is input into the pulse acquisition circuit and the reset signal generation circuit; the feedback clock is input into the feedback pulse generation circuit, the feedback pulse generation circuit outputs feedback pulses, and the feedback pulses are input into the pulse acquisition circuit; the pulse acquisition circuit takes a feedback pulse as clock end input, takes a reference pulse as counting end input, and outputs a phase-locked enable signal; the phase-locked enable signal is output to the phase-locked judgment circuit, and the phase-locked judgment circuit outputs a locking signal after counting reaches a preset value. The scheme provides the detection device which is simple in precision and simple in structure.

Description

technical field [0001] The invention relates to the technical field of phase-locked loops, in particular to a lock detection circuit. Background technique [0002] PLL (Phase Locked Loop) is a phase-locked loop or phase-locked loop, which is used to integrate the clock signal uniformly and make high-frequency devices work normally. PLLs are used for feedback techniques in oscillators. For many electronic devices to function properly, an external input signal usually needs to be synchronized with an internal oscillator signal. General crystal oscillators cannot achieve very high frequencies due to process and cost reasons. When high-frequency applications are required, the corresponding device VCO is used to achieve high-frequency conversion, but it is not stable, so the phase-locked loop can be used to achieve high-frequency conversion. A stable and high-frequency clock signal is achieved. Whether the PLL realizes the locking of the clock frequency determines whether the ...

Claims

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Application Information

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IPC IPC(8): H03L7/085
CPCH03L7/085
Inventor 袁菌
Owner 杭州雄迈集成电路技术股份有限公司
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