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Semiconductor storage device and manufacturing method thereof

A storage device and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems that are contrary to the miniaturization of memory cell arrays

Pending Publication Date: 2021-08-17
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This also goes against the miniaturization of memory cell arrays

Method used

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  • Semiconductor storage device and manufacturing method thereof
  • Semiconductor storage device and manufacturing method thereof
  • Semiconductor storage device and manufacturing method thereof

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no. 1 Embodiment approach

[0023] Figure 1A It is a schematic perspective view illustrating the semiconductor memory device 100a of the first embodiment. Figure 1B It is a schematic plan view showing the laminated body 2 . In this specification, the lamination direction of the laminated body 2 is referred to as the Z direction. One direction intersecting, for example, perpendicular to the Z direction is referred to as the Y direction. One direction intersecting, for example, perpendicular to the Z and Y directions is referred to as the X direction. Figure 2A and Figure 2B Each is a schematic cross-sectional view of a memory cell illustrating a three-dimensional structure. image 3 It is a schematic plan view illustrating the semiconductor memory device 100a of the first embodiment.

[0024] Such as Figure 1A ~ Figure 3 As shown, the semiconductor memory device 100a of the first embodiment is a nonvolatile memory having three-dimensional memory cells.

[0025] The semiconductor memory device 1...

no. 2 Embodiment approach

[0075] Figure 20It is a cross-sectional view showing an example of the configuration of the semiconductor memory device according to the second embodiment. Figure 20 and Figure 5 Similarly, a cross section in a direction perpendicular to the extending direction of the slit SHE when viewed from the lamination direction (Z direction) of the laminate 2 is shown. In the second embodiment, in Figure 20 In the section of , the slit SHE has a middle portion 53 having a width W3 narrower than the width W2 of the bottom thereof. In other words, the slit SHE is wider at the upper opening, but narrows at the middle portion 53, and widens at the bottom. In addition, in the second embodiment, the number of layers of the select gate on the drain side is three layers ( SGD0 to SGD2 ) for convenience.

[0076] The insulating film 50 is filled in the slit SHE from the upper opening to the narrowed middle portion 53 , and has a cavity (void) 51 at the bottom lower than the middle portio...

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Abstract

The invention provides a semiconductor storage device and a manufacturing method thereof, wherein the semiconductor storage device is provided with slits for reliably dividing a plurality of selection gates in the upper part of a memory cell array and can realize miniaturization. According to one embodiment, the semiconductor storage device includes a substrate; a stacked body provided above the substrate, wherein the stacked body includes a plurality of first insulating layers and a plurality of conductive layers that are alternately stacked on top of one another along a vertical direction; a plurality of columnar portions that penetrate the stacked body; a first slit, provided in the vertical direction, that divides one or more of the plurality of conductive layers at least at an upper portion of the stacked body; and a second insulating layer that overlays an opening of the first slit, which forms a cavity.

Description

[0001] [Related applications] [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2020-12717 (filing date: January 29, 2020). This application incorporates all the contents of the basic application by referring to this basic application. technical field [0003] The present embodiment relates to a semiconductor storage device and a manufacturing method thereof. Background technique [0004] In recent years, a semiconductor memory device having a three-dimensional memory cell array in which memory cells are three-dimensionally arranged has been developed. In such a semiconductor memory device, slits are provided in the upper part of the memory cell array in order to divide the select gates. [0005] The slit is formed in the laminated film of the insulating layer and the conductive layer and the columnar portion in the memory hole. However, materials that are difficult to control etching such as metal materials ar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11565H01L27/1157H01L27/11582H01L23/48H01L23/528H01L21/768
CPCH01L23/481H01L23/5283H01L21/76805H01L21/76838H10B43/35H10B43/10H10B43/27H10B43/40H01L21/32139H01L21/31116H01L21/31144H01L21/32136H10B43/50
Inventor 鹿嶋孝之佐藤弘康
Owner KIOXIA CORP
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