Method for forming interconnection structure
A technology of interconnection structure and barrier layer, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems affecting the stability and reliability of semiconductor devices
Active Publication Date: 2021-09-07
中芯国际集成电路制造(深圳)有限公司 +1
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- Abstract
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- Claims
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Problems solved by technology
[0003] The purpose of the present invention is to solve the problem in the prior art that the interconnection structure formed by the formation method of the interconnection structure affects the stability and reliability of the semiconductor device
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[0040] The implementation of the present invention will be illustrated by specific specific examples below, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention will be presented in conjunction with a preferred embodiment, it does not mean that the features of the invention are limited to this embodiment. On the contrary, the purpose of introducing the invention in conjunction with the embodiments is to cover other options or modifications that may be extended based on the claims of the present invention. The following description contains numerous specific details in order to provide a thorough understanding of the present invention. The invention may also be practiced without these details. Also, some specific details will be omitted from the description in order to avoid obscuring or obscuring the gist of the present invent...
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Abstract
The invention discloses a method for forming an interconnection structure, which comprises the steps of forming a first adhesion barrier layer on the bottom and part of the side wall surface of a first groove and the bottom and part of the side wall surface of a second groove, taking the first adhesion barrier layer as a mask, and etching dielectric layers on the side portion of the first groove and the side portion of the second groove. When etching processing is carried out, a structure that the top surface of the residual dielectric layer on the second region is higher than the top surface of the residual dielectric layer on the first region can be formed through transverse etching processing. Through the structure, the height difference between the top surface of a first conductive filling layer and the top surface of a second conductive filling layer is reduced in the subsequent etching process, and the stability and the reliability of the device can be effectively improved. The first adhesion barrier layer and the second adhesion barrier layer can protect the dielectric layer and prevent a protective layer material or a groove filling material layer from diffusing into the dielectric layer.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming an interconnection structure. Background technique [0002] In the manufacturing process of semiconductor integrated circuits, the interconnection process is a common processing process, and the interconnection process is usually used to form structures such as metal interconnection lines. The existing interconnection process usually includes, for example, forming a barrier layer on the substrate, and Forming trenches on the barrier layer, and depositing trench filling materials (such as metal materials used to form metal interconnections) in the trenches, etc., and usually requires chemical mechanical polishing (CMP) to remove Excess barrier and trench fill material. In the CMP process, because the barrier layer and the trench filling material layer in the area with a large trench size are generally more likely to be ground thinner, the difference be...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L21/768
CPCH01L21/76802H01L21/76816H01L21/76831H01L21/76877H01L21/76883
Inventor 纪登峰金懿
Owner 中芯国际集成电路制造(深圳)有限公司