Reducing latch count to save hardware area for dynamic huffman table generation

A Huffman coding, dynamic technique used in instrumentation, computing, data transformation, etc., to solve problems such as area power and expensive timing/wiring

Pending Publication Date: 2021-09-07
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Sequencing symbol counts (frequency) during the process is expensive in terms of area (number of latches and width comparators required), power, and timing / wiring considerations

Method used

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  • Reducing latch count to save hardware area for dynamic huffman table generation
  • Reducing latch count to save hardware area for dynamic huffman table generation
  • Reducing latch count to save hardware area for dynamic huffman table generation

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Embodiment Construction

[0028] Various embodiments of the invention are described herein with reference to the associated drawings. Alternative embodiments of the invention may be devised without departing from the scope of the invention. In the following description and drawings, various connections and positional relationships (eg, above, below, adjacent, etc.) are set forth between elements. Unless stated otherwise, such connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limited in this regard. Accordingly, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be a direct or indirect positional relationship. Furthermore, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein.

[0029] The following definitions and abbreviations are used ...

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PUM

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Abstract

Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.

Description

Background technique [0001] This invention relates to digital computer systems, and more particularly, to digital data compression and decompression schemes employed in digital computer systems. [0002] Digital computer systems perform data compression to achieve more efficient use of limited storage space. Computer systems typically include hardware components called compression accelerators that accept requests for work or data from a host system to compress or decompress one or more blocks of the requested data. When designing an accelerator to perform compression, there is a trade-off between the size of the input data to be compressed compared to the possible compression ratio and the latency incurred by the compressed data. [0003] Compression accelerators typically utilize the "DEFLATE" algorithm, which is a lossless compression scheme that combines a Lempel-Ziv (eg, LZ77) compression algorithm with a Huffman coding algorithm to perform compression. The computationa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M7/40H03M7/30
CPCH03M7/405H03M7/4062H03M7/3086H03M7/6011H03M7/6058G06F5/01G06F5/012H03M7/40
Inventor B·阿巴利A·米什拉S·普萨拉
Owner IBM CORP
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