Inter-core communication method
An inter-core communication and orientation technology, applied in the field of inter-core communication, can solve the problems of not being able to maximize sharing, reducing the utilization of shared memory space, and not being able to apply for shared memory.
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Embodiment 1
[0045] figure 1 It is a flow chart of the inter-core communication method provided by the embodiment of the present invention. Such as figure 1 As shown, the inter-core communication method in this embodiment includes:
[0046] Step 1: Receive the memory block application request from the sender. The memory block application request includes: sending orientation flag, receiving orientation flag and user data length.
[0047] Step 2: traverse the target memory block according to the memory block application request, and determine the first memory block. The target memory block is a plurality of divided memory blocks obtained by randomly dividing the shared memory space by the main core; the first memory block is a divided memory block greater than or equal to the memory required by the sender.
[0048] Step 3: Determine the offset address of the user data according to the first memory block and the memory block application request.
[0049] Step 4: The sender communicates ...
Embodiment 2
[0083] In this embodiment, an inter-core communication method is introduced in detail by taking a sender and a receiver as examples.
[0084] In Embodiment 2, the main core (manager) is the C1 core, the sender is the C2 core, and the receiver is the C3 core, and the C2 core needs to send the message "CMD=0x10, DATA=hello world" to the C3 core, shared memory The total space is 20KB=20*1024B, and the shared memory space is divided into 160 64B small memory blocks and 10 1024B large memory blocks. The basic format definition of each memory block data storage is shown in Table 2:
[0085] Table 2 Basic format of data storage
[0086] send bearing sign receiving bearing sign user data length User data
[0087] Among them, the first three fields constitute the control field, and the total number of bytes occupied is 4B, among which the number of bytes occupied by the sending position mark is 1B, the number of bytes occupied by the receiving position mark is 1B,...
Embodiment 3
[0102] In this embodiment, an inter-core communication method is introduced in detail by taking one sender and two receivers as an example.
[0103] In Embodiment 3, the main core (manager) is the C1 core, the sender is the C2 core, the receiver is the C3 core and the C4 core, and the C2 core needs to send the message "CMD=0x10, DATA=hello world" to the C3 core and C4 core. The quad-core bit flags and shared memory base address definition (take 32-bit address as an example) are shown in Table 5:
[0104] Table 5 Quad-core bit flags and shared memory base address definitions
[0105] nuclear sequence number bit flag Shared memory base address C1 0x01 0x60000000 C2 0x02 0x80000000 C3 0x04 0xA0000000 C4 0x08 0xC0000000
[0106] Except for the above, others are the same as in Embodiment 2, and will not be repeated here.
[0107] Such as image 3 As shown, the process of communication between the three cores is:
[0108] (1) C1 initi...
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