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Dynamic capacity expansion method and system for cache under multi-CPU co-package architecture based on advanced package technology

An advanced packaging technology and high-speed cache technology, which is applied in the field of dynamic expansion of high-speed cache, can solve problems such as packaging difficulties and increased cost of CPU chip casting.

Pending Publication Date: 2021-09-14
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to solve the problems of increasing the CPU chip casting cost and packaging difficulties caused by the expansion of the cache, and proposes a new CPU cache structure design that can dynamically expand the capacity

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  • Dynamic capacity expansion method and system for cache under multi-CPU co-package architecture based on advanced package technology
  • Dynamic capacity expansion method and system for cache under multi-CPU co-package architecture based on advanced package technology
  • Dynamic capacity expansion method and system for cache under multi-CPU co-package architecture based on advanced package technology

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Embodiment Construction

[0042] In order to make the above-mentioned features and effects of the present invention more clear and understandable, the following specific examples are given together with the accompanying drawings for detailed description as follows.

[0043] In the cache structure design of the present invention, the memory access mode of the CPU chip is divided into the following three types:

[0044] 1. General mode. Under this mode, the memory access behavior of the CPU chip is consistent with that of the CPU chip without using the cache memory structure design of the present invention, that is, it will neither access the cache memory of other CPU chips nor be accessed by other CPU chips. On-chip cache.

[0045] 2. Master mode. In this mode, the CPU chip can access the cache memory of other CPU chips, but the cache memory on its own chip will not be accessed by other CPU chips.

[0046] 3. Slave mode. In this mode, the CPU chip can be accessed by other CPU chips to its on-chip ca...

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Abstract

The invention provides a dynamic capacity expansion method and system for a cache under a multi-CPU co-packaging architecture based on an advanced packaging technology, aims to solve the problems of increase of CPU chip casting cost and difficulty in packaging caused by expansion of the cache, and provides a novel CPU cache structure design capable of dynamically expanding the capacity. In the structure, by designing an interaction mechanism of the caches among different CPUs and by means of a packaging technology, the caches in the chips of the CPUs can access the caches in the chips of the CPUs of the same kind, so that the aim of dynamically expanding the capacity of the caches in the chips of the CPUs is fulfilled, and the cache sharing among the CPUs is realized.

Description

technical field [0001] The invention relates to a high-speed cache structure design in the field of CPU structure design, in particular to a dynamic expansion method and system for high-speed cache under a multi-CPU co-encapsulation architecture based on advanced packaging technology. Background technique [0002] In the era of big data and cloud computing, due to the number of users and the diversification of data sources, more and more loads on the CPU show the characteristics of low computing memory access ratio and unobvious data locality. For example, a graph computing application is a typical application in a data center, which is used to quickly process and respond to growing graph data. However, for graph computing applications, due to the irregular and unstructured characteristics of graph computing loads, the execution behavior of graph computing applications becomes very irregular. Irregular and fine-grained memory access results in extremely low cache hit rate a...

Claims

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Application Information

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IPC IPC(8): G06F30/32G06F12/084G06F12/0877G06F115/12
CPCG06F30/32G06F12/084G06F12/0877G06F2115/12Y02D10/00
Inventor 李晓霖郝沁汾叶笑春范东睿
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI