Arbitration system and arbitration method for synchronous bus memory access

Abstract

The invention discloses an arbitration system and an arbitration method for synchronous bus access, and the system comprises: a storage module which is divided into a plurality of storage units; the arbiters and the cache units, the number of which are consistent with the number of the storage units; the request processing unit that is used for receiving the access request sent by the bus and distributing the access request to the corresponding arbiter, wherein each storage unit, the arbiter and the cache unit form a memory access module; the cache unit is used for buffering an access request and sending a req-buffered control signal to the arbiter; and the arbiter is used for sending a stand control signal to the bus after receiving the req-buffered control signal. According to the invention, the storage units are mutually independent, so that access conflicts are avoided; when the same storage unit is accessed at the same time to generate conflicts, the arbiter and the cache unit which are matched with the storage unit send related control signals, so that a bus can stop initiating an access request, and multiple conflicts are prevented.

Description

technical field [0001] The invention relates to the field of processor internal bus arbitration, in particular to an arbitration system and an arbitration method for synchronous bus memory access. Background technique [0002] The speed and accuracy of the processor's memory access directly affect the processor's work efficiency. Existing technologies often optimize the arbitration algorithm to ensure the accuracy of access, but during the running of large programs, conflicts may occur frequently and arbitration may be triggered. The operation of the arbitration algorithm will reduce the efficiency of the actual execution of the program, thereby increasing the delay and reducing the real-time performance. [0003] The prior art CN102736997B discloses an arbitration method and system for an on-chip interconnection bus. The arbitration system is an arbitration for peripherals, and an arbitration feedback signal is sent to the peripherals to control whether the peripherals can...

AI Technical Summary

Problems solved by technology

However, in this scheme, the bus will always receive memory access requests, which will affect the efficiency of the bus

[0004] To sum up, it is necessary to design an arbitration method for synchronous bus memory access to solve the problem of low memory access efficiency caused by many arbitration conflicts in the prior art

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