Formation method of semiconductor structure

Abstract

The invention provides a forming method of a semiconductor structure. The method comprises the following steps: providing a semiconductor substrate; forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure comprises a first metal layer and a second metal layer deposited in a single deposition step; etching a portion of the second metal layer to form a metal plug in the second metal layer, wherein a first metal layer of the patterned metal structure has a first metal structure below and in contact with the metal plug.

Description

technical field [0001] Embodiments of the present invention generally relate to integrated circuit devices, and more particularly, to multilayer interconnect structures of integrated circuits. Background technique [0002] The integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have resulted in each generation of integrated circuits having smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (eg, the number of interconnect devices per unit chip area) generally increases as geometric dimensions (eg, the smallest component or circuit that can be produced by a fabrication process) shrink. A shrinking process is often beneficial for increasing throughput and reducing associated costs. [0003] Shrinking dimensions also increase the complexity of making and processing integrated circuits. To realize these advances, similar develop...

AI Technical Summary

Problems solved by technology

For example, as the size of the integrated circuit structure continues to shrink, the multilayer interconnection structure becomes denser and increases the contact resistance of the interconnection lines of the multilayer interconnection structure, causing challenges in performance, yield, and cost

Higher junction resistances caused by advanced IC technology nodes can significantly delay (and sometimes block) signals to and from the active lines of integrated circuit devices such as transistors, offsetting the performance improvements of integrated circuit devices in advanced technology nodes

In summary, while existing interconnects are often fit for purpose, they may not fit all needs

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