Architecture and method for NAND memory operations

Abstract

In a method for programming a string of memory cells, a program voltage is applied on a selected word line to program selected memory cells in the string of memory cells. A first pass voltage is applied on a first word line coupled to a first one of the memory cells. A second pass voltage is applied on a second word line coupled to a second one of the memory cells. Further, a third pass voltage is applied on a third word line coupled to a third one of the memory cells. The first, second, and third memory cells are located on a first side of a selected memory cell in the string of memory cells, and the second memory cell is disposed between the first memory cell and the third memory cell. The second pass voltage is higher than the first pass voltage and the third pass voltage.

Description

technical field [0001] This application describes embodiments generally related to semiconductor memory devices. Background technique [0002] Semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices can lose data when power is turned off. Nonvolatile memory devices retain stored data even when power is removed. To achieve higher data storage densities, semiconductor manufacturers have developed vertical device technologies such as three-dimensional (3D) NAND flash memory technology. A 3D NAND flash memory device is a non-volatile memory device. Contents of the invention [0003] Aspects of the present disclosure provide methods for programming memory devices including strings of memory cells. The memory cell string may include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor, the bottom select gate (BSG) transistor, the memory cell, and the top select...

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Problems solved by technology

Volatile memory devices may lose data when power is turned off

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