A self-calibrating high-precision digital time conversion circuit

Abstract

The invention provides a self-calibrating high-precision digital time conversion circuit. The invention comprises: a digital-to-analog converter DAC, a capacitor array, a switch array composed of a plurality of switches, and an inverter; the digital-to-analog converter DAC is connected to the capacitor array; the capacitor array is connected to the inverter; the inverter is connected to an output end; The digital-to-analog converter DAC, the capacitor array, the inverter, and the ground terminal are respectively provided with switches; the capacitor array includes a fixed-capacity capacitor cap and a variable-capacity capacitor cap_vary; the digital-to-analog converter DAC according to the input representing the time delay The control word charges the capacitor array, and feeds back the current change of the reference current source to the variable capacitor cap_vary, thereby compensating and calibrating the capacitance value of the capacitor array; the inverter outputs a clock signal according to the capacitance value of the compensated and calibrated capacitor array . It solves the technical problem in the prior art that the reference current is affected by changes in temperature, process and voltage, resulting in an off-side shift in the output clock signal.

Description

technical field

[0001] The invention relates to digital time conversion circuit technology, in particular to a self-calibrating high-precision digital time conversion circuit, which belongs to the technical field of digital-analog hybrid integrated circuits. Background technique

[0002] In recent years, with the continuous development of technology, phase-locked loop (PLL, Phase Lock Loop) is widely used in communication, AI, Internet of Things, sensors and other applications to generate basic clock signals for RF transceivers, timing control circuits and other circuits middle. It has a crucial impact on the performance of the circuit such as noise.

[0003] According to the type of phase-locked loop, it can be divided into analog charge pump phase-locked loop (CPPLL) and all-digital phase-locked loop (ADPLL). Among them, the analog charge pump phase-locked loop has good phase noise performance, but the design complexity and power consumption are higher than the all-digit...

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