Fractional divider and fractional frequency-division phase locked loop

Abstract

The invention discloses a fractional divider. The fractional divider comprises a conversion module, a phase selection module, a variable integer frequency division module and a D trigger, wherein the conversion module is used for generating a phase selection value and an integer frequency division value according to a fractional frequency division parameter; the phase selection module is used for selecting a phase clock corresponding to the phase selection value from M+1 equiphase clocks and transmitting the selected phase clock to the CK end of the D trigger; the variable integer frequency division module is used for transmitting a signal obtained by performing integer frequency division on a reference phase clock signal in the M+1 equiphase clocks to the D end of the D trigger according to the integer frequency division value; and the D trigger is used for generating a fractional frequency division signal from the Q end of the D trigger according to signals input at the CK end and the D end of the D trigger. Compared with a conventional technology for realizing the fractional frequency-division phase locked loop, the fractional divider has the advantages that quantization noise is not introduced, and the periodic jitter is relatively small.

Description

technical field [0001] The invention relates to a fractional frequency divider and a fractional frequency division phase-locked loop. Background technique [0002] Phase Locked Loop (PLL, Phase Locked Loop) is a frequency and phase synchronization technology realized by the feedback (Feedback) control principle. Its function is to synchronize the clock output by the circuit with its external reference clock. Because of its frequency-locking function to keep the clock synchronized, the phase-locked loop is widely used in the field of signal transmission. [0003] The phase-locked loop can generate a large number of discrete frequencies with the same stability by taking a high-stability and high-precision standard frequency signal through four arithmetic operations such as addition, subtraction, multiplication, and division, as well as frequency multiplication, frequency division, and frequency mixing. like figure 1 Shown is the basic circuit structure of the phase-locked lo...

AI Technical Summary

Problems solved by technology

After doing so, the area of ​​the fractional frequency division phase-locked loop becomes larger, the loop response time increases and the phase tracking ability of the input signal decreases, and the noise suppression ability of the voltage-controlled oscillator VCO in the loop decreases

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