Fractional divider and fractional frequency-division phase locked loop

A technology of fractional frequency divider and fractional frequency division, which is applied in the direction of electric components and automatic power control, etc., which can solve the problem of decreased noise suppression ability of voltage-controlled oscillator VCO, larger area of ​​fractional frequency division phase-locked loop, and increased response time And other issues

CN104601171AInactive Publication Date: 2015-05-06SHANGHAI SUNPLUS TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2015-05-06
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a fractional divider. The fractional divider comprises a conversion module, a phase selection module, a variable integer frequency division module and a D trigger, wherein the conversion module is used for generating a phase selection value and an integer frequency division value according to a fractional frequency division parameter; the phase selection module is used for selecting a phase clock corresponding to the phase selection value from M+1 equiphase clocks and transmitting the selected phase clock to the CK end of the D trigger; the variable integer frequency division module is used for transmitting a signal obtained by performing integer frequency division on a reference phase clock signal in the M+1 equiphase clocks to the D end of the D trigger according to the integer frequency division value; and the D trigger is used for generating a fractional frequency division signal from the Q end of the D trigger according to signals input at the CK end and the D end of the D trigger. Compared with a conventional technology for realizing the fractional frequency-division phase locked loop, the fractional divider has the advantages that quantization noise is not introduced, and the periodic jitter is relatively small.
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Description

technical field

[0001] The invention relates to a fractional frequency divider and a fractional frequency division phase-locked loop. Background technique

[0002] Phase Locked Loop (PLL, Phase Locked Loop) is a frequency and phase synchronization technology realized by the feedback (Feedback) control principle. Its function is to synchronize the clock output by the circuit with its external reference clock. Because of its frequency-locking function to keep the clock synchronized, the phase-locked loop is widely used in the field of signal transmission.

[0003] The phase-locked loop can generate a large number of discrete frequencies with the same stability by taking a high-stability and high-precision standard frequency signal through four arithmetic operations such as addition, subtraction, multiplication, and division, as well as frequency multiplication, frequency division, and frequency mixing. like figure 1 Shown is the basic circuit structure of the phase-locked lo...

Examples

Embodiment Construction

[0106] In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0107] Figure 5 The content shown illustrates the principle of integer frequency division. When Divider Num represents the integer frequency division of the frequency divider, that is

[0108] Divider Num=N

[0109] Among them, N is an integer, T VCO Represents the period of the voltage-controlled oscillator VCO output clock, K represents the count of the rising edge of the frequency-divided signal (the upward arrow in the figure), and the frequency division result is in

[0110] Time=K(T VCO ×N)

[0111] The output signal will have a rising edge at any time.

[0112] Promoted by the above integer frequency division principle, such as Image 6 As shown, if the frequency division number of the frequency divider is a decimal, that is

[0113]...