Satellite modem synchronization interface data processing system and data processing method

Abstract

The invention relates to a satellite modem synchronous interface data processing system and a data processing method. The system includes a direct digital frequency synthesizer module (DDS module), a clock control module, and a first-in-first-out data buffer module (FIFO buffer module). The invention controls the working clock frequency of the V.35 synchronous interface through the clock control module, so that the number of data in the FIFO buffer module is stable within a certain range, and will not overflow or read empty, thereby ensuring the stable transmission of the synchronous interface data; In the DTE working mode, the clock control module and the DDS module do not work, and the service rate of the modem is increased to make it greater than the V.35 synchronous interface working clock generated by the DTE equipment, and the gap between the service rate and the clock frequency is compensated by the form of empty packets. If the difference is poor, and correspondingly filter out empty packets at the demodulation end, to ensure that the synchronous interface transmits normal data.

Description

technical field [0001] The invention relates to the technical field of satellite communications, in particular to a satellite modem synchronization interface data processing system and a data processing method. Background technique [0002] V.35 is commonly used to support long-range high-speed synchronous interfaces between DTE and different types of data service unit (DSU) connections in digital transmission facilities, and is often used in packet switches, routers, remote bridges and gateways, etc. It also has a very important role in the satellite modulator, and the satellite modulator has a synchronous interface, which is of practical significance for reducing the number of devices in the application and increasing the stability of the system. [0003] The information rate supported by common satellite modems is from 2.4kbps to more than 10Mbps. Different information rates need to input and output data streams of corresponding rates from V.35, which requires clock and d...

AI Technical Summary

Problems solved by technology

[0005] Since the V.35 working clock and the read / write rate of the modem will not be strictly in the same frequency and phase, there will always be a certain error. After a certain period of time, the FIFO will read empty or overflow, resulting in synchronous interface out of sync or bit error.

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