Method, device and system for determining abnormal test working conditions of chips and related equipment

Abstract

The embodiment of the invention provides a method, device and system for determining abnormal test working conditions of chips, and related equipment. The method comprises the steps of: obtaining the test data of at least two target chip sets in a plurality of chip sets, testing the corresponding chip failure data for multiple times under test working conditions; based on the test data of each target chip set, respectively determining relational data of chip failure data of each target chip set along with the change of the test time; and determining an abnormal chip set from the at least two target chip sets based on the relation data of each target chip set, and determining the test working condition of the abnormal chip set as an abnormal test working condition. According to the method, device and system for determining the abnormal test working conditions of the chips and the related equipment provided by the embodiment of the invention, the efficient and accurate determination of the abnormal test working conditions of the chips is realized, and a basis is provided for accurate chip failure test.

Description

technical field [0001] The embodiments of the present application relate to the field of chip technology, and in particular to a method, device, system and related equipment for determining abnormal test conditions of a chip. Background technique [0002] Chip failure testing (such as early failure testing) is a kind of chip testing, which tests the chip by simulating the working scene of the chip to screen out the failed chips, so as to perform the failure analysis of the chip. When performing the failure test of the chip, different test conditions (for example, different test voltages, etc.) may be applied to the chip, so as to determine the failed chips that fail under different test conditions. However, if the test conditions are unreasonably selected, it is very likely that the test conditions of the chip will exceed the safe test conditions of the chip, so that the normal working scene of the chip cannot be accurately simulated, which will lead to the failure mechanism...

AI Technical Summary

Problems solved by technology

However, if the test conditions are unreasonably selected, it is very likely that the test conditions of the chip will exceed the safe test conditions of the chip, so that the normal working scene of the chip cannot be accurately simulated, which will lead to the failure mechanism of the chip during the failure test. The failure mechanism of the chip in the normal working scene is inconsistent, resulting in inaccurate failure test of the chip

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