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Method for managing requests for access to a random access memory and corresponding system

A random access memory, memory technology, applied in static memory, read-only memory, digital memory information and other directions, can solve problems such as unfavorable consumption

Pending Publication Date: 2021-12-17
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] As a result, some operations performed by the processor last longer, which is disadvantageous in terms of consumption, especially in low-voltage operating modes intended to have lower consumption

Method used

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  • Method for managing requests for access to a random access memory and corresponding system
  • Method for managing requests for access to a random access memory and corresponding system
  • Method for managing requests for access to a random access memory and corresponding system

Examples

Experimental program
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Embodiment Construction

[0053] figure 1 A system SYS is illustrated, comprising a random access memory MM, typically static or dynamic, connected to a central processing unit CPU, eg a processor, by means of a memory interface MM_IF. The term "random access memory" is here understood in a general way, ie a random access memory MM may eg consist of one or more random access memories. The random access memory MM is powered by the power supply voltage Vdd.

[0054] The processing unit CPU is clocked by a clock signal HCLK having a frequency Freq.

[0055] The connection between the processing unit CPU and the memory interface MM_IF is realized via a bus BS, for example of the "Advanced High Performance Bus" AHB type, or more generally via a bus corresponding to the "Advanced Microcontroller Bus Architecture" (AMBA) standard to fulfill.

[0056] Likewise, the connection between the memory interface MM_IF and the random access memory MM is realized via the memory bus BS_MM.

[0057] The system SYS th...

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Abstract

Embodiments of the present disclosure relate to a method for managing requests to access a random access memory, and a corresponding system. A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from French Patent Application No. 2006167, filed June 12, 2020, the content of which is hereby incorporated by reference in its entirety to the fullest extent permitted by law. technical field [0003] Embodiments and implementations relate to the field of microelectronics, and more particularly relate to, for example, random access memory ("RAM") type, dynamic random access memory ("DRAM") type, or static random access memory ("SRAM") type ) type of random access memory access management field. Background technique [0004] A conventional electronic device includes a processor connected to a random access memory, eg by means of a bus and a memory interface. The processor can issue access requests for reading or writing to the random access memory via the bus and the memory interface. [0005] In general, the performance of random access memories degrades as the supply voltage decre...

Claims

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Application Information

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IPC IPC(8): G06F3/06
CPCG06F3/0604G06F3/0614G06F3/0622G06F13/1689Y02D10/00G11C7/1063G11C7/1069G11C7/1096G11C7/222G11C16/3404G06F13/4243
Inventor C·伊瓦J-M·格里尔-马弗瑞
Owner STMICROELECTRONICS SRL
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