DAC with concentric parallelogram wiring and output impedance compensation

Abstract

The invention discloses a DAC with concentric parallelogram wiring and output impedance compensation, and belongs to the technical field of integrated circuits. The method mainly comprises a digital signal input module, a dynamic element matching decoder, a delay equalizer, a digital zero adjuster, an output impedance compensation module and a current source integration module; and the current source integration module is used for respectively arranging all subunits of high-order most significant bits of each unary and all subunits of high-order middle significant bits of each unary into uniformly distributed and concentric parallelograms. The DAC is high in output linearity and small in mismatch error and time sequence skew error, and the integration area can be effectively reduced.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a DAC with concentric parallelogram wiring and output impedance compensation. Background technique [0002] Traditional non-cascaded current cell DACs have the problems of low output impedance affecting the linearity of the DAC, large mismatch errors, and large timing skew errors. [0003] In the prior art, although there are many switching sequence methods that can determine the switching sequence of the current unit to reduce the mismatch error, this solution has the phenomenon of complex and uneven wiring, which will lead to differences between different current units. timing skew and mismatch errors caused by small transistors. Although the drive can be increased to mitigate timing skew, this increases switch current and power dissipation. Contents of the invention [0004] In view of the problems existing in the prior art, the present application ma...

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Problems solved by technology

[0002] The traditional non-cascaded current cell DAC has the problems of low output impedance affecting the linearity of the DAC, large mismatch errors and large timing skew errors

[0003] In the prior art, although there are many switching sequence methods that can determine the switching sequence of the current unit to reduce the mismatch error, this solution has the phenomenon of complex and uneven wiring, which will lead to differences between different current units. Timing skew between and mismatch errors caused by small transistors

Although drive can be increased to mitigate timing skew, this increases switch current and power dissipation

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