Integrated circuit non-pessimistic path analysis method for GPU accelerated calculation

Abstract

The invention discloses an integrated circuit non-pessimistic path analysis method for GPU accelerated calculation. The method comprises the steps of circuit structure flattening, circuit structure layering preprocessing, multi-GPU parallel candidate path generation and global candidate path merging. The multi-GPU parallel candidate path generation comprises the steps of multi-GPU task allocation, delay grouping initialization, parallel delay propagation, parallel progressive candidate path generation and parallel local candidate path pre-merging. According to the invention, by introducing equivalent transformation of an algorithm and a data structure, dense calculation in non-pessimistic time sequence analysis is completed in parallel on a plurality of GPUs, and data and control scheduling work among the GPUs is completed by using a CPU. Through cooperation of a single CPU-multi-GPU heterogeneous calculation model, compared with an original CPU algorithm, the performance can be improved by dozens of times, the calculation cost of non-pessimistic path analysis is greatly reduced, and the invention can be popularized and applied to the technical field of chip design automation.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design automation, and relates to static timing analysis technology of integrated circuits, in particular to an integrated circuit non-pessimistic path analysis method using CPU-GPU heterogeneous acceleration calculation, which ensures accurate static timing analysis results of integrated circuits Under the premise, the efficiency of integrated circuit path analysis is improved. Background technique [0002] Static timing analysis is an important method step in chip design. In this step, chip design automation software will check all paths in the design for timing violations, and report a series of paths that need attention in order of violation degree. The specific process is also called path analysis. Paths with timing violations will seriously affect the operating efficiency and stability of the chip. Therefore, in the automated process of chip design, static timing analysis, as a c...

AI Technical Summary

Problems solved by technology

[0005] To sum up, the existing non-pessimistic accurate static timing analysis technology has the characteristics of large amount of calculation, low calculation efficiency, and poor parallel ability, which limits the application of static timing analysis in chip design optimization

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