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FPGA-based fast data information sorting method and system, equipment and storage medium

A technology of quick sorting and data information, applied in data classification, processing input data, etc., can solve the problems that cannot be sorted into dynamic storage problems, can not greatly reduce resource usage, sorting efficiency, etc., to reduce resource usage , improve sorting efficiency, improve the effect of operating efficiency

Active Publication Date: 2022-01-07
NAT SPACE SCI CENT CAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, existing methods cannot transform the sorting problem into a dynamic storage problem, nor can they greatly reduce resource usage and improve sorting efficiency

Method used

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  • FPGA-based fast data information sorting method and system, equipment and storage medium
  • FPGA-based fast data information sorting method and system, equipment and storage medium
  • FPGA-based fast data information sorting method and system, equipment and storage medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0061] figure 2 The correspondence between the address and the data area sorted without duplicate data sequence array;

[0062] For the data sequence to be sorted, it is recorded as the array {2, 10, 8, 3, 9, 5, 7, 4}, according to step 1), the cache width is 1bit, the cache depth is 10 storage area, as Cache; When power-on, initialize all data regions within the cache to 0. When the arrangement array is entered, according to step 2), the first data point data 2 is read from the outside, which is written as the cache address 2, and the cache address 2 corresponds to 1, and the cache address 2 and data will be District 1 conducts mapping, and deposits the established cache, and sets the maximum value data register and the minimum value data register according to step 3) and writes 2; then repeat step 2), read the second data point from the outside Data 10, as a cache address, write the data area corresponding to the cache address 10 to 1, repeat step 3), update the maximum value d...

Embodiment 2

[0064] image 3 The correspondence between addresses and data areas are derived by repeated data sequence array;

[0065] For the data sequence to be sorted, it is recorded as the descending data {2, 10, 8, 10, 3, 3, 9, 5, 7, 2, 4, 2}, according to step 1), establish a cache width of 4BIT, cache The storage area of ​​the depth is 10, as a cache, when power-on, initializes all data regions within the cache to 0. When the arrangement array is entered, according to step 2), the first data point data 2 is read from the outside, which is placed as the cache address 2; the data area corresponding to the read cache address 2 is placed in a temporary register. At this time the value is 0, add this value to 1, write back the data area corresponding to the cache address 2; simultaneously set the maximum value data register and the minimum value data register, and write 2; then repeat step 2) from the outside first read The second data point data 10 is used as the cache address, reads the da...

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Abstract

The invention belongs to the technical field of data sorting, and particularly relates to an FPGA-based fast data information sorting method. The method comprises the following steps: 1) determining the size of an internal cache of a to-be-sorted data sequence, and establishing the cache; 2) reading the i-th data point in the to-be-sorted data sequence from the outside, mapping the read i-th data point and the corresponding data area one by one, and storing the data points in the established cache one by one; 3) when the ith data point is read in in the step 2), arranging a maximum value data register and a minimum value data register in the FPGA, and correspondingly recording the maximum value data point and the minimum value data point in the to-be-sorted data sequence; 4) repeating steps 2) and 3) to obtain a maximum value data point and a minimum value data point in the cached to-be-sorted data sequence; and step 5) according to a required sorting condition, correspondingly sorting the cached to-be-sorted data sequence, reading each data point one by one, and completing sorting.

Description

Technical field [0001] The present invention belongs to the field of data sorting and data processing, in particular, to a fast sorting method, system, device, and storage medium based on FPGA-based data information. Background technique [0002] Data Sort is an essential data processing operation in the field of computer, and is also a very important basic operation in data processing. By sorting, the data can be fully aligned in a certain order, reducing the subsequent operation; data ordering Used to organize data to achieve fast search, there is a vital role in many applications. In computer applications, data is typically designed or descended. [0003] Traditional sorting adopts the sort algorithm, such as selecting sorting, sorting, base sorting or bubble sorting, etc. Traditional sorting algorithms need to first read data from the outside into the FPGA (Field Programmable Gate Array) cache, and then put the data into the register, step by comparison, exchange, return, etc...

Claims

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Application Information

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IPC IPC(8): G06F7/24
CPCG06F7/24
Inventor 冯水春周海刘一腾卞春江张彪李辉
Owner NAT SPACE SCI CENT CAS
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