Memory device and preparation method thereof

A storage device and storage block technology, applied in the storage field, can solve the problems of occupying a large space and unfavorable storage device size, and achieve the effect of reducing the plane occupied space and minimizing the size

Pending Publication Date: 2022-01-07
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In this way, the storage device in the above-mentioned traditional technical solution needs to occupy a large space to integrate the above-mentioned various parts of the structure, which is not conducive to minimizing the size of the storage device

Method used

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  • Memory device and preparation method thereof
  • Memory device and preparation method thereof
  • Memory device and preparation method thereof

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Embodiment Construction

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

[0039] In the description of the present disclosure, the word line decoder is also described as X-DEC, and the bit line decoder can be described as bit line selector, bit line multiplexer or Y-MUX, which are used for memory array The positioning of most of the storage units for further reading and writing operations on the storage units.

[0040] In describing the present disclosure, it is to be understood that the terms "center", "longitudinal", "transverse", "length", "width",...

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Abstract

The invention discloses a memory device and a preparation method thereof, the memory device comprises a first chip and a second chip, the second chip is stacked above the first chip along a third direction, the first chip comprises a memory array, the memory array comprises at least one memory block, and the memory block is arranged on the first chip. The second chip comprises a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder which are electrically connected with the storage block; a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block and a second word line decoder block are constructed to be located in an overlook projection area of a storage block in a second chip, so that the occupied area after a first chip and a second chip are stacked can be reduced; and therefore, the plane occupied space of the memory device is reduced, and the minimum size of the memory device can be realized.

Description

technical field [0001] The present application relates to the field of storage technologies, in particular to a storage device and a manufacturing method thereof. Background technique [0002] Such as figure 1 As shown, the memory device in the conventional technical solution includes multiple memory arrays 510, multiple local bit line decoders 520, multiple word line decoders 540, multiple global bit line decoders 530 and peripheral circuits 550, Wherein, the configuration area of ​​the memory array 510, the configuration area of ​​the local bit line decoder 520, the configuration area of ​​the word line decoder 540, the configuration area of ​​the global bit line decoder 530 and the configuration area of ​​the peripheral circuit 550 do not overlap each other. For example, the construction area of ​​the local bit line decoder 520 is located at one side of the construction area of ​​the corresponding memory array 510, and the word line decoder 540 is located at the construc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/18G11C8/14H01L25/00H01L25/18
CPCG11C7/18G11C8/14H01L25/18H01L25/50G11C5/025G11C5/063H10B41/10H10B43/10G11C8/08G11C8/10
Inventor 郑钟倍
Owner WUHAN XINXIN SEMICON MFG CO LTD
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