Method and device for simulating chemical mechanical polishing process of multi-layer interconnection structure

Abstract

The invention provides a method and a device for simulating a chemical mechanical polishing process of a multi-layer interconnection structure. Comprising the following steps: calculating to obtain a graphic area height of each position of a lower-layer structure of the semiconductor interconnection structure and a blank area height of the lower-layer structure; subtracting the height of the blank area from the height of the graphic area at each position to obtain a difference value which is used as an unevenness characterization parameter height difference value of each position; superposing the height difference value of the unevenness characterization parameter into the single-layer CMP model to obtain a new model; and performing chemical mechanical polishing simulation on the upper layer structure of the semiconductor interconnection structure by using the new model. Therefore, the single-layer CMP model can be corrected to obtain a new model; as the new model considers the lamination effect of the lower layer structure of the semiconductor interconnection structure on the upper layer structure, a more accurate simulation prediction result of the upper layer structure can be obtained, and the prediction precision of chemical mechanical polishing according to the simulation model is improved; and in the design stage, possible defects are avoided, the period from design to manufacturing of the product is shortened, and the production yield of the product is cooperatively improved.

Description

technical field [0001] The present application relates to the technical field of semiconductor devices, in particular to a method and device for simulating a chemical mechanical polishing process of a multilayer interconnection structure. Background technique [0002] Chemical Mechanical Planarization (CMP) process simulation is one of the key technologies in the field of Design For Manufacture (DFM) of semiconductor structures, and plays an important role in the design and manufacture of integrated circuits. In the process manufacturing of semiconductor structures, the chemical mechanical polishing process of semiconductor structures can be guided according to the simulation results of the chemical mechanical polishing process. Therefore, in order to pursue higher product yields, the accuracy of the CMP simulation results is also more demanding. high. [0003] At present, many scholars have carried out research on the removal mechanism of chemical mechanical abrasive mater...

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Problems solved by technology

[0004] However, many CMP simulation models such as the DSH CMP model are only suitable for the chemical mechanical polishing simulation of single-layer semiconductor structures. Structures will have uneven areas, see figure 1 As shown in Fig. 1, the underlying structure has a recessed area 101. Due to the unevenness of the underlying structure, the initial height of each area of ​​the upper metal is inconsistent, which increases the complexity of the upper metal CMP simulation process, which is called the stacking effect.

Since the current single-layer CMP model does not take into account the stacking effect of the lower structure on the upper structure, it may lead to lower accuracy of the simulation results

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