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DMA transmission system and method applied to NVMe SSD

A transmission system and transmission method technology, applied in the field of computer data transmission, can solve the problems of inability to continuously transmit by itself, large delay in command processing, and suboptimal bus bandwidth utilization, so as to shorten the processing delay and improve the bus bandwidth. Utilization, improve the effect of IOPS

Pending Publication Date: 2022-02-08
SHANDONG SINOCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the traditional NVMe SSD Controller, a single NVME IO command is often used to configure a single DMA, and after the DMA transfer is completed, the firmware operation at the software level will reply to the Host with a Completion message. This method has a greater impact on command processing. Delay, plus each NVME IO needs to be configured with DMA separately, it cannot be continuously transmitted by itself, the utilization of bus bandwidth is not optimal, and the data transmission efficiency is low

Method used

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  • DMA transmission system and method applied to NVMe SSD
  • DMA transmission system and method applied to NVMe SSD

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Embodiment 1

[0023] The present invention provides a DMA transmission method applied to NVMe SSD. Before initiating a data transmission of an NVMe IO command, DMA first configures information such as PRP, Command ID, SQ Identifier, and SQ Head Pointer to the DMA descriptor (DMA descriptor ), after the data transmission of the NVMe IO command is initiated, the data transmission is carried out. After the DMA completes the data transmission, it will automatically send a Completion message to the Host. It is not necessary to use the firmware to wait for the DMA to complete before initiating this NVMe IO command to the Host. completion message.

Embodiment 2

[0025] On the basis of Embodiment 1, the DMA descriptor can be extended to a DMA descriptor chain (DMA descriptionchain), such as figure 2 shown.

[0026] The configuration structure of each DMA descriptor is as follows figure 1 As shown, DWORD0 is configured as SQ Identifier, DWORD1 is configured as SQ Head Pointer, DWORD2 is configured as Command ID, DWORD3-4, DWORD5-6 are respectively configured as PRP1, PRP2 (Host memory address), DWORD7-8 are configured as local address (SSD Internal memory address), DWORD9 is configured as Length (length of data to be transmitted), DWORD10-11 is configured as Next Descriptor (next descriptor), and the Next Descriptor content of the last ring DMA descriptor is empty.

[0027] When starting a descriptor, the DMA engine will perform data transmission according to the PRP1, PRP2, LocalAddress, and Length described in the descriptor, such as an NVMe IO Read command, the data transmission to be performed by the DMA engine is from the Local A...

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PUM

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Abstract

The invention provides a DMA transmission system and method applied to NVMe SSD. According to the invention, the advantages of DMA on a hardware level are utilized, and SQ Identifier, SQ Head Pointer and Command ID information are configured for a DMA descriptor firstly, so the DMA can complete message transmission automatically after data transmission is finished, the action of independently starting DMA Engine for each NVME IO command is omitted, firmware operation on the software level is not needed, each command can automatically reply a Completion message, the processing delay of each command is greatly shortened, and IOPS is improved.

Description

technical field [0001] The invention belongs to the field of computer data transmission, and more specifically relates to an application to NVMe SSD. Background technique [0002] NVMe SSD is a solid state drive (Solid State Disk) that follows the Non-Volatile Memory Host Controller Interface Specification (Non-Volatile Memoryexpress). SSD consists of controller and memory. An excellent NVMeSSD controller can make full use of the low latency and parallelism of the PCIE channel, greatly improve the read and write performance of the solid state disk at a controllable storage cost, reduce the high latency caused by the AHCI interface, and completely liberate The ultimate performance of SSDs in the STAT era. [0003] In the data interaction between NVMe SSD and Host, DMA is an indispensable data transmission method. The way the controller DMAs determines the performance of the SSD. In the traditional NVMe SSD Controller, a single NVME IO command is often used to configure a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/28
Inventor 段好强李瑞东王璞吴斌乔子龙
Owner SHANDONG SINOCHIP SEMICON
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