Fast divider and operating method thereof

Abstract

The invention discloses a fast divider and an operating method thereof. The fast divider comprises an obtaining module which is used for obtaining dividend data and divisor data, and initializing a temporary result value and an ordinal number of iterations according to the dividend data and the divisor data; an initial processing module is used for determining a first significant digit of the dividend data and a second significant digit of the divisor data; a shift number determination module is used for determining the maximum left shift number according to the highest digit number, the first significant digit number and the second significant digit number of the divider; a shift module is used for performing left shift on the current temporary result value according to the maximum left shift number and determining the current ordinal number of the number of iterations as the maximum left shift number; a calculation module is used for calculating according to the current temporary result value and the current ordinal number of the number of iterations by using a non-recovery remainder algorithm corresponding to the highest digit of the divider. under the condition that the calculation result is still accurate, the calculation period is obviously shortened, the consumed time is greatly reduced, and the efficiency of division calculation is effectively improved.

Description

technical field [0001] The invention relates to the field of electronic communication, in particular to a fast divider and its operating method. Background technique [0002] At present, the division calculation performance is one of the important performance indicators to measure the embedded control chip. At the same time, the application of the embedded control chip has high requirements for the real-time performance of the algorithm and the cost of the chip. Currently, most embedded devices use integer numbers for real-time division. Operation, the divisor algorithm generally adopted by FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) general-purpose plastic divider includes the method of restoring the remainder and the method of not restoring the remainder. [0003] Among them, the restorative remainder method has the problem that the calculation cycle is long and not fixed, which greatly restricts the performance of the divider; The number of ...

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Problems solved by technology

[0003] Among them, the restorative remainder method has the problem that the calculation period is long and not fixed, which greatly restricts the performance of the divider; The number of clocks in the calculation cycle is fixed and corresponds to one of the above integer digits, but in actual applications, when the integer digits of the division data are not fixed or the number of effective digits of the division data is small, using the non-recovery remainder method will prolong the integer digits instead. The calculation cycle of the second division operation reduces the calculation efficiency, especially not conducive to large-scale division operations

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