Dynamic ping-pong stack type data rearrangement implementation method based on DDR3 (Double Data Rate 3)
A technology of ping-pong stack and data rearrangement, which is applied in the direction of electrical digital data processing, static memory, digital memory information, etc., can solve the problem that the instantaneous large amount of data cannot be processed, and achieve strong real-time system response, large dynamic range, and dynamic The effect of balance and flexibility
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[0028] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
[0029] The present invention is realized by utilizing the FPGA platform to read and write two clusters of DDR3 memories plugged in. The number of pulse repetitions in a coherent processing interval (CPI) is configured as N, the number of beams in a single pulse repetition period (PRT) is L, and the number of distance units in a single pulse repetition period is M.
[0030] The principle of data rearrangemen...
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