Convolution hardware acceleration method and convolution hardware acceleration circuit

Abstract

The invention provides a convolution hardware acceleration method and a convolution hardware acceleration circuit. The convolution hardware acceleration method comprises the following steps: segmenting a feature map into a plurality of map blocks; during segmentation, the column width of the segmented image blocks is matched with the number of the MAC operation units, and the row height of the segmented image blocks is the maximum row number which can be accommodated by the internal storage module; reading data required by a block and a corresponding convolution kernel for convolution operation in sequence; extracting the extraction data of the image block and the corresponding convolution kernel in sequence; and performing convolution operation and outputting an operation result to an external storage module. By adopting the convolution hardware acceleration method provided by the invention, a smaller internal cache area can be used for supporting feature maps with any resolution to carry out convolution operation; by adopting the block segmentation mode, the utilization efficiency of the MAC operation unit is relatively high, the reading of boundary data in the vertical direction can be reduced as much as possible, and the convolution operation speed is further improved.

Description

technical field [0001] The invention relates to the technical field of convolutional neural network and chip design, in particular to a convolutional hardware acceleration method and a convolutional hardware acceleration circuit. Background technique [0002] Convolution neural network (CNN) is widely used in target recognition, target detection and other application fields. Currently, as the depth of the neural network and the amount of input feature map data increase, the amount of convolution operations continues to increase. The convolution operation of CNN can be performed through a dedicated chip to speed up the calculation speed. However, the design of a dedicated chip for convolution calculation of CNN will face two problems, one is how to increase the parallelism of the operation to improve the calculation efficiency, and the other is how to reduce the read and write bandwidth of the memory to save calculation power consumption. [0003] Therefore, how to provide ...

AI Technical Summary

Problems solved by technology

However, the design of a dedicated chip for CNN convolution calculations will face two problems. One is how to increase the parallelism of operations to improve computing efficiency, and the other is how to reduce the read and write bandwidth of the memory to save computing power consumption.

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