A convolution hardware acceleration method and convolution hardware acceleration circuit

Abstract

The invention provides a convolution hardware acceleration method and a convolution hardware acceleration circuit. The convolution hardware acceleration method includes: dividing the feature map into multiple tiles; when splitting, the column width of the split tiles matches the number of MAC operation units, and the row height of the split tiles is as high as the internal storage module can The maximum number of rows that can be accommodated; the data required for convolution operation of a block and the corresponding convolution kernel are read in order; the extracted data of the block and the corresponding convolution kernel are sequentially extracted; and Convolution operation and output operation result to external storage module. Adopting the convolution hardware acceleration method provided by the present invention can use a smaller internal buffer area to support feature maps of any size resolution for convolution operations; adopting such a block segmentation method makes the utilization efficiency of the MAC operation unit higher , and can reduce the reading of boundary data in the vertical direction as much as possible, and further improve the operation speed of convolution.

Description

technical field [0001] The invention relates to the technical field of convolutional neural network and chip design, in particular to a convolutional hardware acceleration method and a convolutional hardware acceleration circuit. Background technique [0002] Convolution neural network (CNN) is widely used in target recognition, target detection and other application fields. Currently, as the depth of the neural network and the amount of input feature map data increase, the amount of convolution operations continues to increase. The convolution operation of CNN can be performed through a dedicated chip to speed up the calculation speed. However, the design of a dedicated chip for convolution calculation of CNN will face two problems, one is how to increase the parallelism of the operation to improve the calculation efficiency, and the other is how to reduce the read and write bandwidth of the memory to save calculation power consumption. [0003] Therefore, how to provide ...

AI Technical Summary

Problems solved by technology

However, the design of a dedicated chip for CNN convolution calculations will face two problems. One is how to increase the parallelism of operations to improve computing efficiency, and the other is how to reduce the read and write bandwidth of the memory to save computing power consumption.

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