A low-bit efficient deep convolutional neural network hardware acceleration design method, module and system based on logarithmic quantization

Abstract

The invention discloses a low-bit high-efficiency deep convolutional neural network hardware acceleration design method based on logarithmic quantization, which includes the following steps: S1: Realize low-bit and high-precision non-uniform fixed-point quantization based on logarithmic domain, using multiple quantization The codebook quantizes the full-precision pre-trained neural network model; S2: the range of quantization is controlled by introducing offset shift parameters, and an algorithm for adaptively finding the optimal quantization strategy in the case of extremely low-bit non-uniform quantization, Compensate for quantization errors. The invention also discloses a one-dimensional and two-dimensional pulse array processing module and system using the method. The invention can effectively reduce hardware complexity and power consumption.

Description

technical field [0001] The invention relates to artificial neural network hardware implementation technology, in particular to a logarithmic quantization-based low-bit high-efficiency deep convolutional neural network hardware acceleration design method, module and system. Background technique [0002] Convolutional Neural Network (CNN) is an important mathematical model in Deep Learning (DL), which has a powerful ability to extract hidden features of high-dimensional data. In recent years, it has been used in: target recognition, image In many fields such as classification, drug discovery, natural language processing, and Go, major breakthroughs have been made and the performance of the original system has been greatly improved. Therefore, deep convolutional neural networks have been widely studied by scholars all over the world and widely deployed in commercial applications. [0003] A convolutional neural network with deeper layers and larger parameter scale tends to hav...

AI Technical Summary

Problems solved by technology

However, a fatal shortcoming of the convolutional neural network is that its computational complexity is extremely high, and it requires a huge amount of calculation. It is difficult to achieve real-time calculations on some mobile systems and embedded devices, and convolution operations account for 10% of the total amount of calculations. more than 90 percent

Traditional computers based on serial architectures are difficult to meet the above requirements, so realizing fast convolutional neural network operations with lower hardware power consumption and hardware area has become one of the difficulties

[0004] The direct convolution operation is implemented by introducing a fixed-point or floating-point multiplier based on the multiply-add module, but the hardware complexity of the multiplier is large, and it will consume a lot of area and energy.

In a large-scale neural network, a large number of multiply-add devices are required, and the cost of convolution operations will become very high

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