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Quaternary quantum reversible half adder, full adder, parallel full adder and parallel adder/subtractor circuit

A half adder and full adder technology, applied in the field of multivariate quantum logic, to achieve good scalability and performance, less constant input, and beneficial to effective applications.

Pending Publication Date: 2022-03-18
ANHUI MEDICAL UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0039] The technical problem to be solved by the present invention is how to reduce the hardware complexity, constant input, garbage output and quantum cost of the existing quaternary reversible adder circuit so as to improve the circuit performance

Method used

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  • Quaternary quantum reversible half adder, full adder, parallel full adder and parallel adder/subtractor circuit
  • Quaternary quantum reversible half adder, full adder, parallel full adder and parallel adder/subtractor circuit
  • Quaternary quantum reversible half adder, full adder, parallel full adder and parallel adder/subtractor circuit

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Embodiment Construction

[0080] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are part of the present invention Examples, not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0081]In the present invention, a new design of a quaternary reversible circuit is proposed.

[0082] First, a new quaternary reversible half adder circuit is proposed, the overall circuit diagram is shown in Figure 12 shown. The circuit takes two quaternary numbers A and B as input, and the sum S and the carry C generated by adding them are output.

[0083] The truth table o...

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Abstract

The invention provides a quaternary reversible half adder circuit, which takes two quaternary numbers A and B as inputs, takes a sum S and a sum carry C generated by adding as outputs, and is realized by sequentially connecting and combining four parts of circuits in series and a quaternary quantum Feyman gate, and the output of the front part is used as the input of the next part. In the whole quaternary reversible half adder circuit, 13 1-qudit gates and 24 Muthukrishtan Strud gates are used, the hardware complexity of the quaternary reversible half adder circuit is 24 gamma + 13 epsilon, and the quantum cost of the quaternary reversible half adder circuit is 37. The invention also provides a quaternary reversible full adder circuit based on the quaternary reversible half adder circuit, a quaternary reversible parallel full adder circuit based on the quaternary reversible full adder circuit, and a quaternary reversible parallel adder / subtractor circuit based on the quaternary reversible parallel full adder circuit. Compared with the existing design, the circuit provided by the invention has the advantages of lower quantum cost, lower hardware complexity, lower constant input, lower garbage output and better performance, and is more beneficial to effective application of reversible logic design.

Description

technical field [0001] The invention relates to the design field of high-performance reversible circuits in the field of multivariate quantum logic, in particular, it relates to quaternary quantum reversible half adders, full adders, parallel full adders and parallel adder / subtractor circuits, which can be applied to quantum computers, arithmetic Design of processors and complex circuits. Background technique [0002] Energy dissipation is an important aspect in hardware design. Landauer has shown that, for each bit of information lost in a logic calculation, an amount of energy dissipated of at least KTln2 joules, where K is Boltzmann's constant and T is the absolute temperature at which the calculation is performed. Bennett points out that, for quantum circuits, to dissipate zero energy, computations must be information-lossless or reversible. A gate is reversible if the input vector can be specifically retrieved from the output vector and there is a one-to-one correspon...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/502G06N10/20
CPCG06F7/502G06N10/00
Inventor 汤其妹
Owner ANHUI MEDICAL UNIV