Column selection signal unit circuit, bit line sensing circuit and memory

Abstract

The invention discloses a column selection signal unit circuit, a bit line sensing circuit and a memory. The column selection signal unit circuit comprises four column selection units; each bit line comprises 4 * N input and output ports, 4 * N bit line connection ports and a control port; control ports of the first column selection unit and the fourth column selection unit are connected with a first column selection signal, control ports of the second column selection unit and the third column selection unit are connected with a second column selection signal, and bit line connection ports of the first column selection unit and the third column selection unit are connected with 8 * N bit lines of the first storage unit group; bit line connection ports of the second column selection unit and the fourth column selection unit are connected with 8 * N bit lines of the second storage unit group, and the first storage unit group and the second storage unit group are adjacently arranged. According to the technical scheme provided by the invention, the two adjacent bit lines are connected to different sensing amplifier groups, and when the two adjacent bit lines have reading errors at the same time, error data can be detected and corrected by the error detection and correction circuit.

Description

technical field [0001] The present invention relates to the technical field of storage devices, in particular to a column selection signal unit circuit, a bit line sensing circuit and a memory. Background technique [0002] A dynamic random access memory (Dynamic Random Access Memory, DRAM) includes storage units (storage bits) arranged in an array. Each memory cell includes a transistor and a capacitor. The transistor acts as a switch between the capacitor and the bit line and can be activated by a word line coupled to the control terminal of the transistor. The memory cell can store binary information as charges on the capacitor. And the sense amplifier is connected with the storage unit, and can amplify the weak signal stored in the storage unit, so that the data stored in the storage unit can be correctly written or read. [0003] However, in the manufacturing process of the memory storage array, the capacitors of adjacent memory cells are likely to have defects at the ...

AI Technical Summary

Problems solved by technology

[0005] An embodiment of the present invention provides a column selection signal unit circuit, a bit line sensing circuit, and a memory to solve the problem that the memory generates multi-bit errors that exceed the error correction capability of the ECC

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