Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate, forming a discrete channel structure on the substrate in a device region, forming a power track line in the substrate in a power track region, forming a gate structure across the channel structure on the substrate, and forming a source-drain doped region in the channel structure at two sides of the gate structure, an interlayer dielectric layer is formed on the substrate at the side part of the gate structure and the power supply track line; forming a conductive through hole penetrating through the interlayer dielectric layer located on a part of the power supply track line, and exposing the power supply track line; filling a protective layer in the conductive through hole; forming an interconnection groove penetrating through the interlayer dielectric layer at the top of the source-drain doped region, wherein the protective layer is exposed out of the side wall of the interconnection groove; and forming a conductive plug located in the conductive through hole and a source-drain interconnection layer located in the interconnection groove, wherein the source-drain interconnection layer is in contact with the side wall of the conductive plug. The embodiment of the invention is beneficial to enlarging the process window for forming the conductive through hole and the interconnection groove.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] Logic chips are made up of standard cells. The size of the standard cell depends on the metal pitch, the height of the standard cell, the polysilicon pitch, and whether it is a single diffusion block (SDB) or a double diffusion block (DDB). Chip scaling has been driven by metal pitch (MP) and polysilicon pitch (PP) scaling for many years, but MP scaling is challenged by lithographic process limits and increased resistance. And due to device issues, polysilicon pitch scaling has slowed down. The introduction of Design Process Co-Optimization (DTCO) has made compressing standard cell heights the primary scaling option. As the cell height gradually shrinks, the number of fins for a single device per cell also gradually decreases, which will also result i...

AI Technical Summary

Problems solved by technology

However, forming conductive plugs (Via-BPR) for electrically connecting buried power rails presents a major challenge

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