Chip packaging structure, forming method and electronic equipment

Abstract

The invention discloses a chip packaging structure, a forming method and electronic equipment, the packaging structure comprises a semiconductor substrate, and at least a first chip and a second chip are mounted on the first surface of the semiconductor substrate; the protection structure is located on the first surface of the semiconductor substrate and comprises at least a first space and a second space, the first space is a first groove, the second space is a closed cavity, and a first depth from the bottom of the first groove to an opening is larger than a second depth from the bottom to the top in the closed cavity; the first chip is located at the bottom of the first groove, and the second chip is located at the bottom of the closed cavity. By means of the first groove with the first depth larger than the second depth and the closed cavity, the first chip located in the first groove can be exposed to achieve light transmission, and meanwhile the second chip with the requirement for air tightness is still located in the closed cavity to meet the air tightness requirement.

Description

technical field [0001] The present application relates to the field of semiconductor packaging, in particular to a chip packaging structure, forming method and electronic equipment. Background technique [0002] With the increasing integration of electronic chips, the complexity of chip packaging continues to increase. Chips with different functions have different requirements for packaging. Some chips have higher requirements for airtightness and require airtight packaging, while some chips require better exposure and need to be exposed. [0003] In the prior art, for chips that require airtightness and exposure at the same time, epoxy resin cofferdams are usually used to form a specific airtight space on the PCB (Printed Circuit Board, printed circuit board) when packaging, and pass The glass cover forms a specific exposure area to meet the requirements of chip airtightness and exposure. The chip integration realized by the substrate process has a large package volume an...

AI Technical Summary

Problems solved by technology

[0004] In view of this, the present application provides a chip packaging structure, forming method and electronic equipment to solve the problem that the existing chip requires airtightness and exposure at the same time, the volume of the substrate package is large, the integration degree is low, and the epoxy resin The problem that the cavity cannot meet the airtightness requirements

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