Closed-loop control structure for isolating circuit in anti-fuse FPGA (Field Programmable Gate Array)
A technology of isolation circuit and closed-loop control, applied in the direction of conversion equipment without intermediate conversion to AC, can solve the problems of chip response speed and working timing, and achieve the effect of solving the speed problem of chip response
Pending Publication Date: 2022-04-08
58TH RES INST OF CETC
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Problems solved by technology
[0005] The purpose of the present invention is to provide a closed-loop control structure for the isolation circuit in the antifuse FPGA, to solve the problem of chip response speed and working sequence after the system is powered on, reduce system power consumption, and reduce the output ripple of the charge pump. Avoid the impact of charge pump output ripple on the system power supply
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[0028] A closed-loop control structure for isolation circuits in antifuse FPGAs proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
[0029] Such as figure 1 , a schematic diagram of the isolation circuit in the antifuse FPGA for high and low voltage isolation between high voltage and low voltage, isolation transistor 1 and isolation transistor 2 are the isolation circuits used in the antifuse FPGA device, and the isolation tube control circuit is responsible for isolating transistor 1 and isolation transistor 2 on and off. When the antifuse FPGA is programmed...
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The invention discloses a closed-loop control structure for an isolation circuit in an anti-fuse FPGA, and belongs to the field of integrated circuits. According to the invention, the 1 # charge pump is adopted to control the on-off of the NMOS transistor HVN1 switch, and the gate capacitor voltage of the isolation circuit is charged to be close to the voltage value of the chip power supply through the chip power supply, so that the problem of slow boosting of the 2 # charge pump under the condition of large output load capacitance is solved. And when the output voltage value of the 2 # charge pump reaches a certain threshold value, the 1 # charge pump is turned off, the control switch of the NMOS transistor HVN1 is turned off, and the output of the 2 # charge pump is prevented from reversely charging the chip power supply. When the output voltage value of the second charge pump reaches a certain threshold value, the oscillator works in a frequency reduction mode, the power consumption of the second charge pump is reduced, and therefore the power consumption of the system is reduced. When the output voltage value of the 2 # charge pump reaches a certain threshold value, the voltage stabilizing circuit is started, and the output ripple of the secondary charge pump is reduced.
Description
technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a closed-loop control structure used for isolation circuits in antifuse FPGAs. Background technique [0002] Antifuse FPGA is a highly reliable programmable gate array circuit, which has the advantages of non-volatility, low power consumption, high integration, and stable performance. It is widely used in military and aerospace fields with high reliability and high security. Due to its special application fields, such circuits abroad are often embargoed and technically blocked. [0003] Due to the important role of antifuse FPGA, research and technical research on key technologies including antifuse FPGA design technology, testing technology, programming method, and programmer design technology have been carried out in China. [0004] The invention provides a closed-loop control structure suitable for the isolation circuit in the antifuse FPGA. Contents of the inve...
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Login to View More IPC IPC(8): H02M3/07
CPCY02D10/00
Inventor 马金龙赵桂林代志双曹靓蔺旭辉杨霄垒孙杰杰
Owner 58TH RES INST OF CETC