Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate is provided, a to-be-etched material layer is formed on the substrate, a plurality of sacrificial layers which are separated from one another are formed on the to-be-etched material layer, and a first opening is formed between every two adjacent sacrificial layers; forming side wall material layers on the bottom and side wall surfaces of the first opening and the top surface of the sacrificial layer; forming a protective layer on the surface of the side wall material layer; a first graphical layer is formed on the protective layer, first graphical openings are formed in the first graphical layer, and one or more first openings are exposed out of the first graphical openings; forming a barrier layer in the exposed first opening, wherein the top surface of the barrier layer is lower than the top surface of the sacrificial layer; removing the protective layer; removing the side wall material layer on the bottom surface of the first opening and the top surface of the sacrificial layer; and removing the sacrificial layer, and forming a second opening between the remaining side wall material layers. According to the invention, the stability and precision of pattern transmission are improved, so that the performance of the semiconductor structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid growth of the semiconductor integrated circuit (integrated circuit, IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits smaller in size, higher in circuit precision, and development in the direction of higher complexity. [0003] During the development of integrated circuits, usually while the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) gradually decreases, which increases accordingly. Difficulty and complexity of integrated circuit fabrication. [0004] Currently, semiconductor structures are formed with poor performance at ever-s...

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Problems solved by technology

[0003] During the development of integrated circuits, usually while the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) gradually decreases, which increases accordingly. Difficulty and complexity of integrated circuit manufacturing

[0004] Currently, semiconductor structures formed with poor performance at shrinking technology nodes

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