Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for determining test coverage rate for circuit design and information processing system

A technology of test coverage and circuit design, applied in the direction of electrical digital data processing, computer-aided design, special data processing applications, etc., can solve problems such as death, customer return, etc.

Pending Publication Date: 2022-05-13
NXP USA INC
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Missing coverage is more likely to cause problems later on a system than a uniformly distributed undetected defect that does not represent a system-level coverage loss
For critical and other markets, test coverage gaps / gaps can create defects that go unscreened, resulting in customer returns, or in worst case serious safety issues that could result in death if not caught in time

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for determining test coverage rate for circuit design and information processing system
  • Method for determining test coverage rate for circuit design and information processing system
  • Method for determining test coverage rate for circuit design and information processing system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0048] Conventional test coverage analysis tools typically provide abstract test coverage metrics based on the number of testable and untestable nodes. For example, consider the following scenario: A design / chip includes a total of 1,000,000 testable nodes, which are connectors of logic cells. The total number of testable nodes can be defined as the total number of nodes in the design (or area of ​​interest) minus the total number of non-testable nodes in the design (or area of ​​interest). Nodes may not be testable for various reasons such as but not limited to architectural constraints. In this example, 920,000 nodes have been tested and 80,000 nodes have not been tested. Conventional test coverage analysis tools will typically use these tested / untested node counts only at the module level to determine - in this example - that the analyzed tests have 92% test coverage. Income percentage P cov Indicates the probability that the test program screens for defects, where:

[...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A test coverage of a circuit design may be determined by obtaining node testability data and physical location data for each of a plurality of nodes in the circuit design. Based on the node testability data and the physical location data for each node of the plurality of nodes, it is determined that one or more low test coverage areas within the circuit design include untested nodes. Test coverage data is generated for the circuit design, the test coverage data including at least one identification of the one or more low test coverage regions.

Description

technical field [0001] The present invention relates generally to the field of electronic circuit design and, more particularly, to identifying low test coverage areas of integrated circuit designs. Background technique [0002] The design and manufacture of electronic systems such as very large scale (VLSI) integrated circuits (ICs) is an extremely complex and meticulous process. The size and complexity of today's chip / circuit designs make it nearly impossible to design a chip without any errors or to manufacture a chip without any defects. Accordingly, IC designers implement various testing tools and methods to help ensure that the chip's logical design meets the chip's functional specifications and to identify manufacturing defects after the chip is manufactured. Examples of these testing tools and methodologies include functional verification and design for testability (DFT) techniques. Functional verification tools can be used to confirm the functional and logical beh...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398G06F30/392G06F30/394G06F30/396
CPCG06F30/398G06F30/392G06F30/394G06F30/396G01R31/31835
Inventor 阿努拉格·金达尔卡皮尔·纳鲁拉拉胡尔·卡利扬梁洪崑
Owner NXP USA INC