Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate which is provided with a plurality of dummy gate structures; forming an initial dielectric layer on the substrate, wherein the initial dielectric layer is located on the surface of the side wall of the dummy gate structure; the initial dielectric layer is etched to form a dielectric layer, and the top surface of the dielectric layer is lower than the top surface of the dummy gate structure; removing the dummy gate structure, and forming a first opening in the dielectric layer; forming a gate structure material film in the first opening and on the surface of the dielectric layer; and planarizing the gate structure material film until the top surface of the dielectric layer is exposed to form a gate structure. The method is beneficial to improving the performance of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the decreasing size of semiconductor devices, more and more device units are integrated per unit area, the density of devices is gradually increasing, and the size between devices is decreasing, which also increases the difficulty of manufacturing. As the critical dimension (CD) of integrated circuits shrinks, a "gate-last process" is usually used to form the metal gate. The gate-last process requires forming a gate opening in the dielectric layer and filling the gate opening with a gate material. [0003] However, it is difficult to control the height of the existing metal gates, and the height uniformity of the metal gates is poor, which easily leads to inconsistent resistances of different metal gates and threshold voltage drift. In addition, in the self-aligned contact hol...

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Problems solved by technology

[0003] However, it is difficult to control the height of the existing metal gates, and the height uniformity of the metal gates is poor, which easily leads to inconsistent resistance of different metal gates and threshold voltage drift.

In addition, in the self-aligned contact hole formation process, the filling material in the planarized contact hole usually stops on the protective layer on the metal gate, and the non-uniform metal gate will easily lead to poor uniformity of the self-aligned contact hole. The performance of the resulting semiconductor device is poor

[0004] Therefore, the performance of existing semiconductor devices is poor

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