Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, and the manufacturing method of the semiconductor element comprises the steps: providing a substrate which comprises a logic element region and a memory element region; forming a memory stack structure on the memory element region, and forming a protection layer covering the top surface and the side wall of the memory stack structure; then forming a first interlayer dielectric layer on the protective layer, and performing an etching back manufacturing process after grinding to remove a part of the first interlayer dielectric layer and a part of the protective layer on the top surface of the memory stack structure; a second interlayer dielectric layer is formed on the first interlayer dielectric layer and directly contacts the protective layer. An upper contact structure is formed through the second interlayer dielectric layer and the protective layer on the top surface of the memory stack structure and contacts the memory stack structure.

Description

technical field [0001] The invention relates to a semiconductor element and a manufacturing method thereof, in particular to a magnetoresistive random access memory (MRAM) element and a manufacturing method thereof. Background technique [0002] Magnetoresistive random access memory (MRAM) is a new type of memory that has received high attention in recent years. It integrates the advantages of various types of memory, such as memory comparable to static random access memory (SRAM). Acquisition speed, non-volatility and low power consumption of flash memory (flash), high density and durability of dynamic random access memory (DRAM), and can be integrated with the current semiconductor back-end manufacturing process (Back end online, BEOL) , so it has the potential to become a memory mainly used in semiconductor chips. [0003] The magnetoresistive random access memory includes a memory stack structure disposed between upper and lower interconnection structures. The memory s...

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Problems solved by technology

For example, an interlayer dielectric layer covering the top surface of the memory stack structure or a passivation layer used to passivate or protect the memory stack structure may be used in the etching process for forming the upper contact structure for electrically connecting the memory stack structure. In the process of etching, the bottom of the upper contact structure is notched or not etched, which affects the contact quality between the memory stack structure and the top contact plug, resulting in abnormal data writing or reading of the magnetoresistive random access memory.

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