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Wear allocation in nonvolatile memory

A non-volatile, memory array technology for memory systems, instrumentation, climate sustainability, and more

Pending Publication Date: 2022-07-08
WESTERN DIGITAL TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Then it can be determined to swap PBA for LBA

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  • Wear allocation in nonvolatile memory
  • Wear allocation in nonvolatile memory
  • Wear allocation in nonvolatile memory

Examples

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Embodiment Construction

[0038]Instead of using the metadata in the address mapping table to direct the data indicated by the LBA for a write operation to a specific physical PBA and track the LBA / PBA mapping, the present disclosure uses a Multilevel Interconnect Network (MIN) to correlate or map LBAs to PBAs . In one example, the LBA indicated at the MIN input maps to the PBA indicated at the MIN output. Three alternative embodiments are presented for changing the MIN in order to swap the PBA assigned to the LBA:

[0039] 1. PBAs can be randomly selected for allocation to LBAs experiencing heavy traffic, and the non-blocking MIN can be adjusted accordingly to record this changed allocation.

[0040] 2. A random switching element within the MIN along a path through the MIN representing a mapping from a certain PBA to an LBA can switch from a first state, such as a shoot-through state, to a second state, such as a cross-over state, or vice versa.

[0041] 3. The switching elements along the path for ...

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Abstract

The invention provides a method, a circuit and a system for managing wear leveling in a non-volatile memory. First, an original physical block address (PBA) for a logical block address (LBA) for a write operation may be received. The original PBA is one of a set of PBAs for a data block of a non-volatile memory array. Each of the PBAs may be uniquely mapped to a particular LBA using a multi-level interconnect network (MIN). A swap PBA may then be determined for the LBA. The swap PBA may be selected from the set of PBAs that are uniquely mapped using the MIN. The MIN may then be configured to map the LBA to the swap PBA. Finally, data of a first data block stored at the original PBA may be swapped with data of a second data block stored at the swap PBA.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims priority to US Application Serial No. 17 / 213,005, filed March 25, 2021, which claims priority to US Provisional Patent Application Serial No. 63 / 075,462, filed September 8, 2020 rights and interests, both of which are incorporated herein by reference. Background technique [0003] Some data stored in non-volatile memory devices can be accessed and overwritten frequently, while other data can be written once and maintained in that state for a relatively long period of time. Physical non-volatile memory structures that experience frequent access can be electrically and mechanically stressed to a greater extent than areas that are infrequently accessed, and therefore, if no action is taken to mitigate this unbalanced use, the Experiencing higher levels of wear during life. [0004] A "wear level" refers to a measure of the conditions under which a collection of memory cells performs their designed ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/02
CPCG06F12/0246G06F2212/7201G06F2212/7202Y02D10/00G06F12/0873G06F3/0619G06F3/0679G06F2212/7211G06F3/0635
Inventor K·K·古纳姆
Owner WESTERN DIGITAL TECH INC