Interconnection structure and forming method thereof
A technology of interconnection structure and metal interconnection structure, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of bad plasma damage, electrical failure, performance degradation, etc.
Pending Publication Date: 2022-07-26
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology
However, during the anisotropic etch process of patterning openings through the overlying insulating layer, previously formed metal interconnect structures can suffer from undesirable plasma damage
Such plasmonic damage can lead to electrical failure or degradation of underlying electrical connections such as field effect transistors
Method used
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[0086] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first and second features are in direct contact, and may also include an embodiment between the first and second features Embodiments where additional features are formed such that the first and second features are not in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for the sake of brevity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.
[0087] Additionally...
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Abstract
An interconnect structure and a method of forming the same, the interconnect structure may include: an interconnect surface dielectric material layer over a substrate; the first metal interconnection structure is embedded in the interconnection surface dielectric material layer and comprises a first metal barrier liner and a first metal filling material part; and an overlying dielectric material layer. Openings in the overlying dielectric material layer may be formed throughout the region of the first metal barrier liner and outside the region of the first metal fill material portion to reduce plasma damage. A second metal interconnect structure may be formed in the opening that contacts a top surface of the first metal barrier liner. An entirety of a top surface of the first metal fill material portion contacts a bottom surface of the overlying dielectric material layer.
Description
technical field [0001] The present disclosure relates to an interconnect structure and a method of forming the same. Background technique [0002] Typically, an anisotropic etch process can be used to pattern openings through the overlying insulating layer. However, previously formed metal interconnect structures may suffer from undesirable plasma damage during the anisotropic etch process through the patterned openings in the overlying insulating layer. Such plasma damage can lead to electrical failure or reduced performance of underlying electrical connection elements such as field effect transistors. SUMMARY OF THE INVENTION [0003] Some embodiments of the present disclosure provide an interconnect structure including: an interconnect surface dielectric material layer and a first metal interconnect structure. An interconnect level dielectric material layer is over the substrate. The first metal interconnect structure is embedded in the interconnect surface dielectri...
Claims
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IPC IPC(8): H01L23/528H01L21/768
CPCH01L23/528H01L21/76841H01L2221/1073H01L21/76816H01L23/5283H01L23/53223H01L21/76843H01L23/5226H01L24/05H01L2224/05027H01L2224/05559H01L2224/04042H01L24/03H01L23/535H01L23/53266H01L21/3212H01L21/76895H01L21/7684H01L21/76805
Inventor 江政鸿巫幸晃刘家玮
Owner TAIWAN SEMICON MFG CO LTD