Method for manufacturing high-density semiconductor storage device

Abstract

A method for fabricating a high-density semiconductor memory device which can reduce chip size and increase memory device characteristics. The present invention provides SOI type memory device. The capacitor is embedded in the insulator below the semiconductor wafer and the transistor is formed after the formation of the capacitor. As a result, the degradation of the transistor can be prevented, sufficiently increase the capacitor surface area, and provide fully planarized surface during the processing steps.

Description

technical field [0001] The present invention relates to a method of manufacturing high-density semiconductor memory devices, and more particularly to a method of manufacturing high-density dynamic random access memories (DRAMs) utilizing SOI (silicon-on-insulator) by bonding two-body silicon wafers. Background technique [0002] As the bit density of semiconductor memory quadruples every three years, its operating speed also increases. Such development of semiconductor memory has made possible an operation speed of 1 Gb (gigabit) DRAM (Dynamic Random Access Memory) or 1 GHz (Giga Hertz). [0003] In DRAM devices, the 8F used in the era of 64K DRAM density 2 The memory cell size has been used so far. From the perspective of the bit line arrangement relative to the sense amplifier, this 8F 2 The memory cell is called a folded bit line cell structure. 8F 2 is the minimum theoretical cell size of the folded bit line cell structure. Here, F represents the minimum feature si...

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