Integrated circuit implementing method and circuit of shortened cyclic code correcting interpretation algorithm

Abstract

This invention relates to a method and a circuit for realizing IC of correcting error decoding algorithm with a shortening circulation code including a. adjoint computing unit computes the adjoint S(x) according to the input code R(x) b. sending the said every adjoint S(x) to related correction unit separately to be modified to get the adjoint coefficient P(x) c. inputting each adjoint coefficient P(x) to error position positioning unit which will output error correction bit E(x) at the place the error happens d the said error correction bit E(x) and information symbol R(x) via R level buffer are processed with XOR and output symbol Y(x). The circuit includes a buffer memory, several adjoint S(x) computing units, related adjoint correction units, XOR and an error position positioning unit.

Description

[0001] Technical Field The present invention relates to encoding and decoding and integrated circuit technology, in particular to an integrated circuit (ASIC) implementation method and circuit of an error correction decoding algorithm for shortening cyclic codes. Background technique [0002] The error correction decoding of shortened codes (hereinafter referred to as BCH codes) is a cyclic code that can correct multiple random errors proposed by Hocquenghem in 1958 and Bose and Ray-Chaudhuri in 1960. It is an error correction capability Extremely strong error correction code, BCH is the initials of the names of the three. For the BCH code that can correct three or less random errors, it is called BCH-3 decoding. There are various algorithms for implementing BCH-3 decoding, but the basic principles are realized through the following steps: [0003] 1. Calculate the adjoint formula S(x) from the received codeword R(x) and detect errors; [0004] 2. Determine the error positio...

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Problems solved by technology

[0010] This scheme has been improved on the implementation of calculating the error-location polynomial by the adjoint formula (see KraftBCH error-location polynomial decoder, 1994). The purpose of this scheme is to increase the speed, but when calculating the intermediate variable, a large number of multiplication and For division operation, it is very difficult to implement ASIC for multiplication and division on finite fields, especially for division circuits. Therefore, the realization of multiplication and division in this implementation method is through ROM storage. address to get the result of multiplication and division, which has a good effect on increasing the rate for code streams with short codewords, but if the length of codewords is very long, such as 4359 in this example, then use this method To achieve the required ROM (Read Only Memory read-only memory) will be very large, which is too wasteful for resources

[0011] figure 2 The implementation method of is mainly improved in the step of calculating the error position polynomial from the adjoint formula, but in the calculation of the decision vectors a, b, c and δ 1 ,δ 3 ,δ 5 A large number of multiplication and division operations are used. These multiplication and division operations are obtained through ROM addressing to obtain the results of multiplication and division. Therefore, it is very wasteful to use this method for error correction of large data streams. For example, to realize the finite field GF(2 13 ), first store the power of each element on the finite field and the value on the finite field corresponding to each power, and then add the exponents of the two elements to get an exponent when multiplying, according to this From the index to the ROM where the value is stored, the result is found. Although this method fundamentally solves the speed of calculating δ, it causes a great waste of resources.

[0012] To sum up, the realization circuit of the above-mentioned translation algorithm is complicated, the delay is large, the operation speed is low, and there is a certain waste of circuit resources.

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