Memory address producing device, moving station and data read/write method

A memory address, memory technology, applied in static memory, memory system, digital memory information, etc., can solve the problems of difficult manufacturing, cost increase, slow down, etc.

Inactive Publication Date: 2005-08-31
LG INFORMATION & COMM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] However, as mentioned above, prior art encoders have various problems in the column direction address generator
First of all, the two counters and two accumulators in the prior art column direction address generator make the hardware complicated and difficult to manufacture (such as size increase, cost increase, time extension, etc.)
In addition, the initialization of each counter, initial value generator and accumulator at an appropriate time required for the generation of the address generator in the column direction makes the encoding or decoding rate of image data lower or slow down.

Method used

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  • Memory address producing device, moving station and data read/write method
  • Memory address producing device, moving station and data read/write method
  • Memory address producing device, moving station and data read/write method

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Embodiment Construction

[0038] Preferred embodiments of the present invention will be described in detail below with reference to the examples in the drawings. According to a preferred embodiment of the present invention there is disclosed an apparatus for generating a memory address which is a row and / or column directional address of a transposed memory having reduced size, increased speed and simultaneous dual use (dual use), and also discloses the use of the device in a communication system. The preferred embodiment generates memory addresses according to the invention in the desired direction (eg column direction) by shifting the required bit stream, and processes row direction write addresses and column direction read addresses in parallel.

[0039] Figure 5 A block diagram of an apparatus for generating memory addresses according to a first preferred embodiment of the present invention is shown. In the description of the preferred embodiment, it is assumed that all transpose memories describ...

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Abstract

The memory address generator includes a counter (500) which sequentially generates addresses with a predetermined number of bits, to create row addresses. A shifting device shifts the sequential bit addresses by 'n' bits, to create column addresses. The shifting device is a barrel shifter (510). Independent claims are included for a mobile station for coding and transmitting image data, and a method of transmitting data for a transposition memory.

Description

technical field [0001] The present invention relates to transpose memory, in particular to a device for generating memory addresses. Background technique [0002] Transpose memories are used in encoders, decoders or interleavers in mobile communication systems. For a mobile station having an image transmission function, an encoder encodes image data to transmit an image to a counterpart, and a decoder receives the encoded image data and decodes it into original image data. An interleaver is used to minimize burst errors of data transmitted in a CDMA communication system. [0003] The encoder and decoder of the mobile station will be described below. Figure 1 shows a block diagram of a prior art encoder. [0004] As shown in Figure 1, prior art coder is provided with: 2D DCT part 100, is used for receiving image data and carries out discrete cosine transform (DCT) to it twice; Quantization part 110, is used for receiving and quantization from DCT part image data of 100; a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04B1/40G11C7/10G11C8/04H04N7/26H04N7/50
CPCG11C8/04H04N19/00781H04N7/50H04N19/00484G11C7/1018H04N7/26707H04N19/423H04N19/61H04B1/40
Inventor 李柱兴
Owner LG INFORMATION & COMM LTD
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