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Integrated circuit package formed at wafer level

An integrated circuit and wafer-level technology, applied in the direction of circuits, electrical components, electrical solid-state devices, etc., can solve problems such as impossible manufacturing packaging

Inactive Publication Date: 2005-08-31
ATMEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Because wirebonds have a predetermined length and require a minimum spacing between adjacent pads to provide adequate space for the solder tip, the substrate base must be longer than the die, making it impossible to create more compact packages

Method used

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  • Integrated circuit package formed at wafer level
  • Integrated circuit package formed at wafer level
  • Integrated circuit package formed at wafer level

Examples

Experimental program
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Effect test

Embodiment Construction

[0017] Referring to FIG. 1, a silicon wafer 21 has a plurality of microcircuits formed thereon. The microcircuits are arranged in a matrix of individual chips or blocks 24,25. A plurality of aluminum pads 23 are arranged around the perimeter of each chip. In prior art packaging operations, the wafer 21 is typically diced here into individual chips, and each individual chip is subsequently packaged. In the present invention, chips are formed on a wafer, but dicing is not performed until the packaging operation on the wafer is completed, so that the packaging of the chips can be performed at the wafer level.

[0018] refer to figure 2 , shows the cross-section 2 - 2 of the wafer 21 and the aluminum pads 23 placed on the top surface of the wafer 21 . The first step in the packaging process is to re-metallize the aluminum pads 23 to make the pads solderable. Aluminum (often used for wire-bond pads in ICs) is not an ideal metal for solder connections because it oxidizes easily,...

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PUM

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Abstract

An integrated circuit package that is formed at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. A pre-fabricated interposer substrate, made of metal circuitry and a dielectric base, has a plurality of metallized openings which are aligned with metallized wirebond pads on the top surface of a silicon wafer. Solder, or conductive adhesive, is deposited through the metallized openings to form the electrical connection between the circuitry on the interposer layer and the circuitry on the wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

Description

technical field [0001] The present invention relates generally to integrated circuit packaging, and more particularly to ball grid array integrated packages formed at the wafer level. Background technique [0002] The footprint of an integrated circuit package on a circuit board refers to the substrate area occupied by the package. It is often desirable to minimize the footprint and place the packages in close proximity. Ball Grid Array (BGA) packaging has become an increasingly popular packaging type in recent years because it offers high density, a minimal footprint, and a shorter electrical path, which means it is more Semiconductor package types have better performance. [0003] As shown in Figure 9 is a typical BGA package. In the BGA package 110, an integrated circuit chip 122 is mounted on an upper surface of a substrate 112 made of a substrate material by an adhesive. Metal bond wires or wire bond wires 120 connect a plurality of metal die pads 126 formed on the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/12H01L23/485
CPCH01L2924/01015H01L24/10H01L2924/0103H01L2924/01023H01L2924/01082H01L2924/01079H01L2224/48465H01L2924/01068H01L2924/01002H01L2924/14H01L2924/01033H01L2924/01006H01L2924/01029H01L2224/13099H01L2924/01078H01L2924/01057H01L2924/10253H01L2924/01058H01L2924/01075H01L2224/48091H01L2224/73265H01L2924/01013H01L2924/014H01L24/13H01L2224/13H01L2224/023H01L2924/15311H01L2924/181H01L2924/00014H01L2924/00H01L2924/0001H01L2224/32225H01L2224/48227H01L2924/00012H01L23/49816H01L24/97
Inventor K·M·拉姆
Owner ATMEL CORP