Scalable low-latency switch for usage in interconnect structure

Abstract

A scalable low-latency switch extends the functionality of a multiple level minimum logic interconnect structure for usage in computers of all types, networks and communication systems. The multiple level minimum logic interconnect structure employs a data flow technique based on timing and positioning of messages moving through the structure. The scalable low-latency switch is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided while the interconnect structure operates as a 'deflection' or 'hot potato' system in which processing and storage overhead at each node are reduced. The interconnect structure using the scalable low-latency switch employs a method of achieving wormhole routing through an integrated circuit chip by a novel procedure for inserting messages into the chip. Rather than simultaneously inserting a message into each unblocked node on the outer cylinder at every angle, messages are inserted simultaneously into two columns A and B only if an entire message fits between A and B. Messages are inserted into column 0 at time 0. Messages are inserted into column 1 at time t0+tC, where time tc is the time for a first bit of a message to move from column 0 to column 1 on the top level. Messages are inserted into column 2 at time t0+2tC, and so forth. The strategy prevents the first bit of one message from colliding with an interior bit of another message already in the switch. Contention between entire messages is addressed by resolving the contention between the first bit only so that messages wormhole through many cells.

Description

technical field [0001] The invention relates to the interconnect structure of computing and communication systems, in particular to a scalable low-latency switch for multi-layer interconnect structure. Background technique [0002] A longstanding important and unsolved problem in computer science is the lack of a scalable low-latency interconnect structure that can sustain high throughput (high cross-sectional bandwidth) at full load. Existing interconnection designs such as banyon, omega and fat-tree networks, multi-layer grid, torus and hypercube networks lack infinite scaling and low communication load support to varying degrees. Waiting time and high transmission rate. The geometry of these networks was developed by mathematicians in the nineteenth century and earlier, but never attempted to support a method of message sending. [0003] An interconnect fabric and a suitable switch are needed to form an interconnect fabric that is practically infinitely scalable and sup...

AI Technical Summary

Problems solved by technology

[0010] The second lack of interconnection switch technology is that a single switch design cannot support multiple different communication protocols

Pin-limited design is easy to only support communication protocols with small packet lengths such as ATM

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