CMOS I/O offset control circuit

Abstract

The invention provides a CMOS I / O bias control circuit and can work at 3V, 5V or between 3V and 5V without adjusting its structure. The invention is composed of one power source and three amplifiers. In different operational and processing conditions, such as the quick transistor process, change of the environmental temperature or change of the supply voltage, it can provide constant current. The bias control circuit normally provides two bias signals to promote the CMOS transistor I / O.

Description

technical field [0001] The present invention relates to a CMOS I / O bias control circuit, especially a CMOS I / O bias control circuit that does not require a specific input voltage (eg, 3V or 5V). Background technique [0002] In the past, CMOS I / O bias control circuits were required to work at a specific voltage. People expect a bias circuit that can work at two power supply voltages of 3V or 5V without changing the structure of the circuit. It is also desirable that the output of the bias circuit still have a constant rise and fall time (1-2V / ns) over a wide range of variations in supply voltage, ambient temperature, and operating process. [0003] For prior art bias circuits using a fixed 5V input voltage Vcc, see figure 1 (US Patent No.: 4978905). Generally, an output reference voltage is generated by a reference circuit and several transistors. Its main disadvantage is that it cannot work at 3V input voltage, but only at 5V or greater. In addition, its linear operatin...

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Problems solved by technology

Its main disadvantage is that it cannot work at 3V input voltage, and can only work at 5V or greater than 5V

In addition, its linear operating range can only be from 4.5V to 6.5V. When the circuit is in a noisy environment, the anti-power interference rate is low, and the noise of the power supply may be directly injected into the circuit, causing strong jitter

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