Bit reduction device

Abstract

A bit reduction apparatus preventing visual recognition of beat noise while maintaining gradation is presented. The bit reduction apparatus of the invention changes over the bit reduction operation by executing simple discarding process and noise shaping process, on the basis of at least any one of input signal state, user's setting state, and apparatus setting state.

Description

technical field [0001] The present invention relates to a downscaling device for reducing the number of bits of an image signal to ensure its gray scale. Background technique [0002] Generally, in digital signal processing, the more digitized bits, the higher the gray level. However, an increase in the number of bits has a problem of increasing the circuit scale and the number of pins of the device. In digital signal processing, there are various proposals for reducing the number of bits while ensuring gray levels as much as possible, and Japanese Laid-Open Patent Publication No. 2000-224047 is one example. [0003] In addition, as a more general circuit, a bit reduction circuit using an adder and a delay is widely used for noise reduction shaping. This prior art will be described with reference to FIGS. 5 , 6 , and 7 as an example of the prior art. [0004] 5 is a block diagram showing the structure of a prior art example. In this figure, an image quality correction cir...

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Problems solved by technology

On the other hand, in the case of no input, the input signal is a DC "0" signal, and the so-called DC "0" signal is "black". Usually, even if there is noise, it is not conspicuous. However, in the image quality correction circuit 500, the When the bias voltage is added to the image signal (equivalent to the user's adjustment of the enhanced black level), there is a problem that the PWM component is perceived as noise

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