Method for implementing physical design for dynamically reconfigurable logic circuit
A technology of logic circuit and structure design, applied in the field of structural design of dynamic reconfigurable logic circuits, can solve problems such as not being accepted, not having detailed knowledge of FPGA structure and methods, and achieve the effect of saving time
Inactive Publication Date: 2003-08-06
ATMEL CORP
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However, for most designers (who are under pressure to keep pace with the market and may not have detailed knowledge of FPGA architecture and methodology), this architectural design approach will not be acceptable
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[0020] refer to figure 1 , a dynamic reconfigurable logic design using reconfigurable macros is shown including static logic 140 and reconfigurable logic 150 . Each static 140 and reconfigurable 150 logic circuit consists of a circuit macro network. Each macro is a circuit element representing a basic logic resource in the target FPGA structure, such as a logic gate or a memory element. Alternatively, circuit macros may be hierarchical, containing other levels of macros or circuit elements, or both. Macro A141, Macro B142, Macro C143 and Macro D144 constitute a static macro network, while Macro E155 and Macro F156 constitute a reconfigurable macro network. FPGA input 133 is shown as macro A 141 provided to the static logic network. FPGA output 134 is generated from static logic macro C144, while FPGA output 135 is generated from reconfigurable logic macro F156. These macros are interconnected in a dynamically reconfigurable logic design.
[0021] In dynamic reconfigurable...
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A method for implementing the physical design for a dynamically reconfigurable logic circuit. The method is carried out using software that forms a physical design flow to take a design specification from a schematic or high-level description language (HDL) through to FPGA configuration bitstream files. The method involves reading a design netlist (160) that was entered, the design netlist (160) including a set of static macros (140) and a set of reconfigurable macro contexts (150). Then, each of the reconfigurable macros (150) are compiled and an initial device context is placed and routed. The device context is updated by arbitrarily selecting a context for each reconfigurable macro, placing and routing the updated device context and repeating the steps of updating, placing and routing until all of the reconfigurable macro contexts have been placed and routed. Then, after the compilation process is complete, full, partial, and incremental bitstream files are generated.
Description
technical field [0001] The present invention relates generally to programmable logic devices formed on integrated circuits, and more particularly to a method for implementing structural design of dynamically reconfigurable logic circuits. Background technique [0002] Dynamic reconfigurable logic (also known as cache logic) is a digital design technique used to reconfigure programmable logic circuits, such as SRAM-based field programmable gate arrays (FPGAs) and composite programmable logic devices (CPLDs) . Dynamic reconfigurable logic devices utilize the dynamic and partial reconfigurability of SRAM-based FPGAs, and when reconfiguring part of the FPGA logic, the rest of the logic will continue to work without being interrupted. [0003] The principle of dynamically reconfigurable logic is illustrated in FIG. 6, which shows the implementation of a part of logic reconfiguration on an FPGA. Replacement logic 120 is stored in off-chip memory 124 . During reconfiguration, on...
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IPC IPC(8): G06F17/50H01L21/82H03K19/173
CPCG06F17/5054G06F17/5068G06F30/39G06F30/34G06F30/347
Inventor D·A·马康恩耐尔A·V·达萨利M·T·梅森
Owner ATMEL CORP