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Semiconductor device with partical insulator base or partial hollow-base epitaxial silicon structure

A semiconductor and device technology, applied in the field of semiconductor devices

Inactive Publication Date: 2003-08-27
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As mentioned above, SOI has suitability and insuitability for each kind of circuit

Method used

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  • Semiconductor device with partical insulator base or partial hollow-base epitaxial silicon structure
  • Semiconductor device with partical insulator base or partial hollow-base epitaxial silicon structure
  • Semiconductor device with partical insulator base or partial hollow-base epitaxial silicon structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] use Figure 1A A semiconductor device according to Embodiment 1 of the present invention will be described. Figure 1A is a plan view of a semiconductor device having a partial SOI structure.

[0031] As shown, the semiconductor device 1 has a bulk region and an SOI region. Element regions AA1 to AA6 electrically isolated from each other by means of element isolation region STI are provided in the body region and the SOI region. On the element areas AA1 to AA6, MOS transistors TR1 to TR6 are provided, respectively. The MOS transistors TR1 to TR6 have gate electrodes 16a to 16f, respectively. The gate electrodes 16a, 16b, 16d, and 16e of the MOS transistors TR1, TR2, TR4, and TR5 are arranged parallel to the boundary line between the bulk region and the SOI region. Furthermore, the gate electrodes 16c, 16f of the MOS transistors TR3, TR6 are arranged perpendicular to the boundary line between the bulk region and the SOI region.

[0032] The element area AA1 is separat...

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PUM

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Abstract

A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Description

technical field [0001] The present invention relates to a semiconductor device, and particularly relates to a technology that can be used in a system LSI using a SOI (Silicon On Insulator) substrate or a SON (Silicon On Nothing: Epitaxial Silicon On Insulator) substrate. Background technique [0002] SOI has long been known as a structure in which a silicon layer is formed on an insulating film. It has become a hot topic in recent years to reduce the power consumption of logic circuits or to increase the speed of operation by forming semiconductor elements on such SOI. It is expected that SOI will also be used in system LSIs such as mixed DRAMs in the future. [0003] However, in the MOS transistor formed on SOI, the potential of the body region where the channel is to be formed often causes a specific operation phenomenon caused by floating. This phenomenon is called the substrate floating effect. Substrate floating effect causes leakage current and threshold voltage var...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/76H01L21/762H01L21/764H01L21/8234H01L21/8242H01L21/84H01L27/08H01L27/088H01L27/10H01L27/108H01L27/12H01L29/786
CPCH01L21/84H01L27/10861H01L29/78639H01L21/76243H01L27/10873H01L21/823481H01L27/1203H01L27/10894H01L27/1207H10B12/038H10B12/05H10B12/09H01L27/12
Inventor 山田敬佐藤力新田伸一永野元水岛一郎亲松尚人南良博宫野信治藤井修
Owner KK TOSHIBA