Method fo reduce capacitive loading in flash memory X-decoder for accurate voltage control at wordlines and select lines

Abstract

An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

Description

Technical field

[0001] The present invention relates to column decoding used in NOR (NOR gate) flash memory architecture. In particular, it relates to a semiconductor integrated circuit memory device, which includes a device and method for reducing the capacitive load in the flash memory X-decoder so as to correctly control the voltage on the selected word line and the block word line. Background technique

[0002] One type of non-volatile memory device well known in the art, namely "flash EEPROMs", is an important memory device recently proposed that combines the advantages of EPROM density and EEPROM electronic erasability. The flash EEPROMs provide electronic erasable function and small cell size. In the existing flash EEPROM memory device, a plurality of single-transistor core cells are formed on the semiconductor substrate, and each cell includes a P-type conductive substrate, an N-type conductive source region integrated on the substrate, and also integrated on the substrat...

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