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I/O buffer with protective circuit worked on multilevel voltage

A technology for protecting circuits and output buffers, applied in the connection/interface layout of logic circuits, circuits, logic circuits, etc., and can solve problems such as transistor destruction

Inactive Publication Date: 2003-09-24
XIAMEN UNISOC TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when this device is used in a high-voltage environment, undesired high voltages can be generated, causing the destruction of the transistor

Method used

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  • I/O buffer with protective circuit worked on multilevel voltage
  • I/O buffer with protective circuit worked on multilevel voltage
  • I/O buffer with protective circuit worked on multilevel voltage

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Embodiment Construction

[0017] Each part of the present invention will be described in detail below. The following text provides sufficient detail to understand and describe the practice of the present invention, although, of course, a skilled practitioner does not need these details to understand the present invention. In other cases, when describing various implementations of the present invention, in order to avoid unnecessary distraction, we use some well-known structures and functions instead of showing and describing them in detail. For the sake of understanding and convenience, in describing any one embodiment, the same reference numerals and abbreviations designate the same element or act.

[0018] The circuit described here provides an I / O buffer capable of using different supply voltages, in particular at 5, 3.3, 1.8 and 1.3 volts when the I / O buffer must be able to interface with a thin oxide fabricated transistor gate required reliability under the limitation of operating voltage.

[00...

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PUM

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Abstract

This invention relates to an I / O buffer with a protection circuit capable of enduring multistage working voltage with little or no current leakage, its output part is formed by a PMOS transistor and two N channel NMOS transistors in sories. This PMOS transistor is controlled by a protect circuit to prevent generating current leakage.

Description

[0001] related application [0002] This application claims priority to US Provisional Application No. 60 / 362,832, filed March 8, 2002 in the same title in the United States. (1) Technical field [0003] The invention relates to an I / O buffer in an integrated circuit, in particular to an I / O buffer capable of working on multi-level voltages. (2) Background technology [0004] The development trend of integrated circuits is to reduce cost, reduce power consumption and improve performance. The main way to reduce costs is to migrate products to smaller and smaller volumes, reduce die size and increase production. The ever-shrinking device geometries require similarly lower operating voltages. The operating voltage of integrated circuits has dropped from 5 volts, 3.3 volts, and 1.8 volts to the current 1.3 volts. The result - the system needs to be able to work with mixed voltages. In other words, an integrated circuit must be able to interface with other integrated circuits...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H03K19/00H03K19/003H03K19/0175
CPCH03K19/00315
Inventor 范仁永肖照华
Owner XIAMEN UNISOC TECH CO LTD