Control logic for lowering power consumption of cache instructions

Abstract

A control logic for decreasing the power consumption of instruction cache is disclosed. On one side, the index marker memory is accessed in advance by autilizing its gap to obtain the line match and group selection information of next cache line, so only opening one group of data memory can fetch the instruction, resulting in less accesses to the data memory. On another side, a ring history buffer area is used to store the group selection information and address range, obtained by each access to the index marker memory, for reusing them when the program is jumped in the address range, resulting in less accesses to the index marker memory.

Description

technical field [0001] The invention relates to a control logic for reducing power consumption of instruction cache. Background technique [0002] Cache can provide much faster access speed than main memory and has become a necessary component of modern CPU. But at the same time, the cache has also become the main power-consuming part of the chip. In some designs, the power consumption of the cache accounts for more than 30% of the entire chip. In applications that are very sensitive to power consumption, the application of the cache is limited, and the result is often to reduce the capacity of the cache to obtain a compromise effect. [0003] The basic structure of Cache generally consists of two parts: data memory and index mark memory. The following uses an instruction cache in a 32-bit CPU as an example to illustrate its working principle. The cache capacity is 8K bytes, the line size is 16 bytes, and the mapping method is 2-way group associat...

AI Technical Summary

Problems solved by technology

This will inevitably place the index mark memory and data memory on different pipeline beats, thereby increasing the number of pipeline stages and affecting system performance

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