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Method of forming barrier layer

A technology of barrier layer and component layer, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as insufficient thickness of titanium nitride layer

Inactive Publication Date: 2003-10-15
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, if the TiN barrier formed by this conventional process is applied to a high aspect ratio contact, the thickness of the TiN layer at the bottom of the contact is usually insufficient

Method used

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  • Method of forming barrier layer

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Embodiment Construction

[0030] figure 1 is a cross-sectional view of a portion of a semiconductor substrate including a barrier layer in a preferred embodiment of the present invention, first, as figure 1 As shown, a component layer 101 is formed on a semiconductor substrate 100 , and the component layer 101 includes at least one conductive region 102 and at least one isolation structure 103 . The component layer also includes one or more transistor components (not shown), and / or one or more metal layers (not shown). The isolation structure 103 is, for example, a field oxide layer or a shallow trench isolation structure. The interlayer dielectric layer 104 is formed on the substrate 100 and covers the isolation structure 103 and the underlying conductive region 102 . The conductive region 102 may be a polysilicon gate layer or a source / drain region of a transistor, or a metal layer. For silicon-based semiconductor substrates, the dielectric material of the interlayer dielectric layer can be silico...

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Abstract

The present invention discloses the method of forming Ti / TiN layer for contact / dielectric layer opening with high height / width ratio. Before forming a Ti layer with ionic metal plasma and depositinga TiN layer through metal and organic compound chemical vapor deposition, one gas stabilizing step to provide regulated hydrogen, helium, reaction gas source and carrier gas source. The said step can reduce RC lagging and reflecting index of the barrier to improve the performance of contact / dielectric layer plug and device.

Description

technical field [0001] The invention relates to a method for manufacturing an integrated circuit (IC), in particular to a method for manufacturing a barrier layer (Barrier Layer) used in contact plugs and interlayer plugs (Contact / Via Plug). Background technique [0002] In order to meet the ever-increasing complexity and precision requirements of semiconductor integrated circuits, two or more metal interconnect layers (Metal Interconnect Layers) are often formed on a substrate in semiconductor manufacturing. Currently, a contact plug is used to connect the terminal of a metal oxide semiconductor (MOS) part and a metal layer, and a via plug is used to connect two different metal layers. The plug technology used in most very large scale integration (VLSI) processes is tungsten plugs. [0003] Sandwiching another material between two contacting layers, such as tungsten and silicon, prevents mixing of the materials between the two layers. The main function of the third materi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/285H01L21/768
CPCH01L21/2855H01L21/76865H01L21/76843H01L21/28556
Inventor 黄俊智陈太郎
Owner UNITED MICROELECTRONICS CORP